Issued Patents All Time
Showing 26–40 of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9236374 | Fin contacted electrostatic discharge (ESD) devices with improved heat distribution | Robert J. Gauthier, Jr., Rahul Mishra, Souvick Mitra, Mujahid Muhammad | 2016-01-12 |
| 9059278 | High voltage lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) having a deep fully depleted drain drift region | Robert J. Gauthier, Jr., Junjun Li, Rahul Mishra, Souvick Mitra, Mujahid Muhammad | 2015-06-16 |
| 9041127 | FinFET device technology with LDMOS structures for high voltage operations | Robert J. Gauthier, Jr., Junjun Li, Rahul Mishra, Souvick Mitra, Mujahid Muhammad | 2015-05-26 |
| 8760827 | Robust ESD protection circuit, method and design structure for tolerant and failsafe designs | Shunhua T. Chang, Kiran V. Chatty, Robert J. Gauthier, Jr., Junjun Li, Mujahid Muhammad | 2014-06-24 |
| 8674400 | Stress enhanced junction engineering for latchup SCR | Robert J. Gauthier, Jr., Junjun Li, Rahul Mishra | 2014-03-18 |
| 8634172 | Silicon controlled rectifier based electrostatic discharge protection circuit with integrated JFETs, method of operation and design structure | Shunhua T. Chang, Kiran V. Chatty, Robert J. Gauthier, Jr., Mujahid Muhammad | 2014-01-21 |
| 8614489 | Vertical NPNP structure in a triple well CMOS process | Shunhua T. Chang, Kiran V. Chatty, Robert J. Gauthier, Jr., Junjun Li, Rahul Mishra +1 more | 2013-12-24 |
| 8513738 | ESD field-effect transistor and integrated diffusion resistor | Shunhua T. Chang, Kiran V. Chatty, Robert J. Gauthier, Jr., Junjun Li, Rahul Mishra +1 more | 2013-08-20 |
| 8377754 | Stress enhanced junction engineering for latchup SCR | Robert J. Gauthier, Jr., Junjun Li, Rahul Mishra | 2013-02-19 |
| 8363367 | Electrical overstress protection circuit | Shunhua T. Chang, Kiran V. Chatty, Robert J. Gauthier, Jr., Junjun Li, Mujahid Muhammad | 2013-01-29 |
| 8354722 | SCR/MOS clamp for ESD protection of integrated circuits | Shunhua T. Chang, Kiran V. Chatty, Robert J. Gauthier, Jr., Junjun Li, Rahul Mishra +1 more | 2013-01-15 |
| 8350329 | Low trigger voltage electrostatic discharge NFET in triple well CMOS technology | Shunhua T. Chang, Kiran V. Chatty, Robert J. Gauthier, Jr., Junjun Li, Rahul Mishra +1 more | 2013-01-08 |
| 8299533 | Vertical NPNP structure in a triple well CMOS process | Shunhua T. Chang, Kiran V. Chatty, Robert J. Gauthier, Jr., Junjun Li, Rahul Mishra +1 more | 2012-10-30 |
| 8168500 | Double gate depletion mode MOSFET | Richard A. Phelps, Robert M. Rassel, Michael J. Zierak | 2012-05-01 |
| 7902606 | Double gate depletion mode MOSFET | Richard A. Phelps, Robert M. Rassel, Michael J. Zierak | 2011-03-08 |