Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6523097 | Unvalue-tagged memory without additional bits | Marc A. Auslander | 2003-02-18 |
| 6490625 | Powerful and flexible server architecture | Nayeem Islam, Trent R. Jaeger, Vsevolod Panteleenko | 2002-12-03 |
| 6347364 | Schedulable dynamic memory pinning | — | 2002-02-12 |
| 6260130 | Cache or TLB using a working and auxiliary memory with valid/invalid data field, status field, settable restricted access and a data entry counter | — | 2001-07-10 |
| 6202132 | Flexible cache-coherency mechanism | Nayeem Islam, Trent R. Jaeger, Vsevolod Panteleenko | 2001-03-13 |
| 6079004 | Method of indexing a TLB using a routing code in a virtual address | — | 2000-06-20 |
| 6044466 | Flexible and dynamic derivation of permissions | Rangachari Anand, Frederique A. Giraud, Nayeem Islam, Trent R. Jaeger | 2000-03-28 |
| 6044488 | Process for generating a check word for a bit sequence for verifying the integrity and authenticity of the bit sequence | — | 2000-03-28 |
| 6032228 | Flexible cache-coherency mechanism | Nayeem Islam, Trent R. Jaeger, Vsevolod Panteleenko | 2000-02-29 |
| 6009503 | Cache memory indexing using virtual, primary and secondary color indexes | — | 1999-12-28 |
| 5913222 | Color correction method in a virtually addressed and physically indexed cache memory in the event of no cache hit | — | 1999-06-15 |
| 5813046 | Virtually indexable cache memory supporting synonyms | — | 1998-09-22 |
| 5790979 | Translation method in which page-table progression is dynamically determined by guard-bit sequences | — | 1998-08-04 |