Issued Patents All Time
Showing 76–100 of 153 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6275908 | Cache coherency protocol including an HR state | Ravi Kumar Arimilli, John Steven Dodson | 2001-08-14 |
| 6272603 | Cache coherency protocol having hovering (H), recent (R), and tagged (T) states | Ravi Kumar Arimilli, John Steven Dodson | 2001-08-07 |
| 6263407 | Cache coherency protocol including a hovering (H) state having a precise mode and an imprecise mode | Ravi Kumar Arimilli, John Steven Dodson | 2001-07-17 |
| 6247098 | Cache coherency protocol with selectively implemented tagged state | Ravi Kumar Arimilli, John Steven Dodson | 2001-06-12 |
| 6212605 | Eviction override for larx-reserved addresses | Ravi Kumar Arimilli, John Steven Dodson, Derek E. Williams | 2001-04-03 |
| 6212616 | Even/odd cache directory mechanism | Ravi Kumar Arimilli, John Steven Dodson | 2001-04-03 |
| 6195729 | Deallocation with cache update protocol (L2 evictions) | Ravi Kumar Arimilli, John Steven Dodson | 2001-02-27 |
| 6192458 | High performance cache directory addressing scheme for variable cache sizes utilizing associativity | Ravi Kumar Arimilli, John Steven Dodson | 2001-02-20 |
| 6192451 | Cache coherency protocol for a data processing system including a multi-level memory hierarchy | Ravi Kumar Arimilli, John Steven Dodson | 2001-02-20 |
| 6185658 | Cache with enhanced victim selection using the coherency states of cache lines | Ravi Kumar Arimilli, John Steven Dodson | 2001-02-06 |
| 6182201 | Demand-based issuance of cache operations to a system bus | Ravi Kumar Arimilli, John Steven Dodson, Derek E. Williams | 2001-01-30 |
| 6178484 | DCBST with ICBI mechanism to maintain coherency of bifurcated data and instruction caches | Ravi Kumar Arimilli, John Steven Dodson | 2001-01-23 |
| 6175930 | Demand based sync bus operation | Ravi Kumar Arimilli, John Steven Dodson, Derek E. Williams | 2001-01-16 |
| 6173371 | Demand-based issuance of cache operations to a processor bus | Ravi Kumar Arimilli, John Steven Dodson, Derek E. Williams | 2001-01-09 |
| 6161189 | Latch-and-hold circuit that permits subcircuits of an integrated circuit to operate at different frequencies | Ravi Kumar Arimilli, Derek E. Williams | 2000-12-12 |
| 6157980 | Cache directory addressing scheme for variable cache sizes | Ravi Kumar Arimilli, John Steven Dodson | 2000-12-05 |
| 6145059 | Cache coherency protocols with posted operations and tagged coherency states | Ravi Kumar Arimilli, John Steven Dodson | 2000-11-07 |
| 6145038 | Method and system for early slave forwarding of strictly ordered bus operations | John Steven Dodson, Ravi Kumar Arimilli | 2000-11-07 |
| 6141733 | Cache coherency protocol with independent implementation of optimized cache operations | Ravi Kumar Arimilli, John Steven Dodson | 2000-10-31 |
| 6138218 | Forward progress on retried snoop hits by altering the coherency state of a local cache | Ravi Kumar Arimilli, John Steven Dodson | 2000-10-24 |
| 6128707 | Adaptive writeback of cache line data in a computer operated with burst mode transfer cycles | Ravi Kumar Arimilli, John Steven Dodson | 2000-10-03 |
| 6122691 | Apparatus and method of layering cache and architectural specific functions to permit generic interface definition | Ravi Kumar Arimilli, John Steven Dodson, Derek E. Williams | 2000-09-19 |
| 6112270 | Method and system for high speed transferring of strictly ordered bus operations by reissuing bus operations in a multiprocessor system | John Steven Dodson, Ravi Kumar Arimilli | 2000-08-29 |
| 6105112 | Dynamic folding of cache operations for multiple coherency-size systems | Ravi Kumar Arimilli, John Steven Dodson, Derek E. Williams | 2000-08-15 |
| 6101582 | Dcbst with icbi mechanism | Ravi Kumar Arimilli, John Steven Dodson | 2000-08-08 |