Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7486123 | Set/reset latch with minimum single event upset | David Jia Chen | 2009-02-03 |
| 7425855 | Set/reset latch with minimum single event upset | David Jia Chen | 2008-09-16 |
| 7259602 | Method and apparatus for implementing fault tolerant phase locked loop (PLL) | — | 2007-08-21 |
| 7103857 | Method and latch circuit for implementing enhanced performance with reduced quiescent power dissipation using mixed threshold CMOS devices | — | 2006-09-05 |
| 6954086 | Low power data storage element with enhanced noise margin | David Jia Chen | 2005-10-11 |
| 6661121 | Pulse generator with controlled output characteristics | Roger P. Gregor | 2003-12-09 |
| 4274017 | Cascode polarity hold latch having integrated set/reset capability | Eric Lee Carter | 1981-06-16 |