Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and latch circuit for implementing enhanced performance with reduced quiescent power dissipation using mixed threshold CMOS devices

Method and latch circuit for implementing enhanced performance with reduced quiescent power dissipation using mixed threshold CMOS devices

US Patent 7103857 · Granted Sep 5, 2006

Estimated economic value: $3,397,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Set/reset latch with minimum single event upset2009
Set/reset latch with minimum single event upset2008
Method and apparatus for implementing fault tolerant phase locked loop (PLL)2007
Low power data storage element with enhanced noise margin2005
Pulse generator with controlled output characteristics2003
Cascode polarity hold latch having integrated set/reset capability1981