Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8672688 | Land grid array interposer with compressible conductors | Robert F. Florence, Jr., Prabjit Singh | 2014-03-18 |
| 8662931 | Delayed contact action connector | H. John Healey, Prabjit Singh | 2014-03-04 |
| 8282420 | Delayed contact action connector | H. John Healey, Prabjit Singh | 2012-10-09 |
| 7758390 | Large array surface mount technology connector cradle assembly | Michael J. Domitrovits, Prabjit Singh, Joseph George | 2010-07-20 |
| 7547231 | Large array connector for coupling wafers with a printed circuit board | Michael J. Domitrovits, Prabjit Singh | 2009-06-16 |
| 7505251 | Actuation mechanism for mating electronic card interconnect systems | Shawn Canfield, John J. Loparco, Budy D. Notohardjono, Michael T. Peets, John G. Torok | 2009-03-17 |
| 6674297 | Micro compliant interconnect apparatus for integrated circuit devices | Robert F. Florence, Jr., Vincent P. Mulligan, Charles R. Tompkins | 2004-01-06 |
| 6527935 | Process for electroplating pins of an integrated circuit package | Mark A. Brandon, Arden S. Lake, Joseph M. Sullivan | 2003-03-04 |
| 6497805 | Method for shorting pin grid array pins for plating | Arden S. Lake, Joseph M. Sullivan | 2002-12-24 |
| 6214180 | Method for shorting pin grid array pins for plating | Arden S. Lake, Joseph M. Sullivan | 2001-04-10 |
| 6197171 | Pin contact mechanism for plating pin grid arrays | Mark A. Brandon, Arden S. Lake, Joseph M. Sullivan | 2001-03-06 |
| 6051119 | Plating structure for a pin grid array package | Paul F. Findeis, Kenneth R. Idler, Minkailu A Jalloh, Thomas A. Kelly | 2000-04-18 |
| 5800184 | High density electrical interconnect apparatus and method | Lewis S. Goldmann, Joseph M. Sullivan, Charles R. Tompkins | 1998-09-01 |
| 5729148 | Probe assembly | Joseph M. Sullivan | 1998-03-17 |
| 5691467 | Method for mapping surfaces adapted for receiving electrical components | Lewis S. Goldmann | 1997-11-25 |