Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11809982 | Performance and area efficient synapse memory cell structure | Takeo Yasuda, Kohji Hosokawa, Junka Okazawa | 2023-11-07 |
| 11087811 | NVM synaptic element with gradual reset capability | Atsuya Okazaki, Takeo Yasuda | 2021-08-10 |
| 10672471 | Linearly weight updatable CMOS synaptic array without cell location dependence | Masatoshi Ishii, Kohji Hosokawa, Atsuya Okazaki | 2020-06-02 |
| 10490273 | Linearly weight updatable CMOS synaptic array without cell location dependence | Masatoshi Ishii, Kohji Hosokawa, Atsuya Okazaki | 2019-11-26 |