Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10784679 | Electrostatic discharge protection apparatus and integrated circuit with multiple power domains | Bingwu Ji, Yu Xia | 2020-09-22 |
| 6759491 | Simultaneous reverse and normal initiation of ATRP | Krzysztof Matyjaszewski, Jerome Gromada | 2004-07-06 |
| 5807771 | Radiation-hard, low power, sub-micron CMOS on a SOI substrate | Truc Q. Vu, Chen-Chi P. Chang, James S. Cable | 1998-09-15 |
| 5652448 | Nonvolatile memory device | Chen-Chi P. Chang, Truc Q. Vu | 1997-07-29 |
| 5578515 | Method for fabricating gate structure for nonvolatile memory device comprising an EEPROM and a latch transistor | Chen-Chi P. Chang, Truc Q. Vu | 1996-11-26 |
| 5523244 | Transistor fabrication method using dielectric protection layers to eliminate emitter defects | Truc Q. Vu, Maw-Rong Chin | 1996-06-04 |
| 5511036 | Flash EEPROM cell and array with bifurcated floating gates | Joseph E. Farb, Chen-Chi P. Chang | 1996-04-23 |
| 5378909 | Flash EEPROM cell having gap between floating gate and drain for high hot electron injection efficiency for programming | Chen-Chi P. Chang | 1995-01-03 |
| 5343424 | Split-gate flash EEPROM cell and array with low voltage erasure | Chen-Chi P. Chang | 1994-08-30 |
| 5185535 | Control of backgate bias for low power high speed CMOS/SOI devices | Joseph E. Farb, Chen-Chi P. Chang, Maw-Rong Chin | 1993-02-09 |
| 5140390 | High speed silicon-on-insulator device | Chen-Chi P. Chang, Maw-Rong Chin | 1992-08-18 |
| 5137837 | Radiation-hard, high-voltage semiconductive device structure fabricated on SOI substrate | Chen-Chi P. Chang | 1992-08-11 |
| 5047356 | High speed silicon-on-insulator device and process of fabricating same | Chen-Chi P. Chang, Maw-Rong Chin | 1991-09-10 |
| 5024965 | Manufacturing high speed low leakage radiation hardened CMOS/SOI devices | Chen-Chi P. Chang | 1991-06-18 |