Issued Patents All Time
Showing 26–38 of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 4370712 | Memory controller with address independent burst mode capability | Chester M. Nibby, Jr. | 1983-01-25 |
| 4369510 | Soft error rewrite control system | Chester M. Nibby, Jr. | 1983-01-18 |
| 4366538 | Memory controller with queue control apparatus | Chester M. Nibby, Jr. | 1982-12-28 |
| 4366539 | Memory controller with burst mode capability | Chester M. Nibby, Jr. | 1982-12-28 |
| 4361869 | Multimode memory system using a multiword common bus for double word and single word transfer | Chester M. Nibby, Jr. | 1982-11-30 |
| 4359771 | Method and apparatus for testing and verifying the operation of error control apparatus within a memory | Chester M. Nibby, Jr. | 1982-11-16 |
| 4323965 | Sequential chip select decode apparatus and method | Chester M. Nibby, Jr., Dana W. Moore | 1982-04-06 |
| 4319324 | Double word fetch system | Chester M. Nibby, Jr., Dana W. Moore | 1982-03-09 |
| 4302735 | Delay line compensation network | Chester M. Nibby, Jr. | 1981-11-24 |
| 4255852 | Method of constructing a number of different memory systems | Chester M. Nibby, Jr. | 1981-03-17 |
| 4236203 | System providing multiple fetch bus cycle operation | John L. Curley, Richard A. Lemay, Chester M. Nibby, Jr. | 1980-11-25 |
| 4190901 | Printed circuit board apparatus which facilitates fabrication of units comprising a data processing system | Chester M. Nibby, Jr. | 1980-02-26 |
| 4185323 | Dynamic memory system which includes apparatus for performing refresh operations in parallel with normal memory operations | Chester M. Nibby, Jr. | 1980-01-22 |