Issued Patents All Time
Showing 26–50 of 55 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6600492 | Picture processing apparatus and picture processing method | Tetsuya Shimomura, Shigeru Matsuo, Kazuyoshi Koga, Koyo Katsura, Kazushige Yamagishi | 2003-07-29 |
| 6587111 | Graphic processor and data processing system | Atsushi Nakamura, Kazushige Yamagishi | 2003-07-01 |
| 6433782 | Data processor apparatus and shading apparatus | Shigeru Matsuo, Jun Satoh, Masanori Miyoshi, Koyo Katsura, Takashi Sone | 2002-08-13 |
| 6384831 | Graphic processor and data processing system | Atsushi Nakamura, Kazushige Yamagishi | 2002-05-07 |
| 6356269 | Image processing device and system using the same | Keisuke Nakashima, Shigeru Matsuo, Masahisa Narita, Koyo Katsura, Hidehito Takewa +1 more | 2002-03-12 |
| 6333745 | Data processor having unified memory architecture providing priority memory access | Tetsuya Shimomura, Shigeru Matsuo, Koyo Katsura, Tatsuki Inuzuka | 2001-12-25 |
| 6236404 | Perspective projection calculation devices and methods | Ichiro Iimura, Jun Satoh, Takashi Sone | 2001-05-22 |
| 6219062 | Three-dimensional graphic display device | Shigeru Matsuo, Jun Sato | 2001-04-17 |
| 6167497 | Data processing apparatus and register address translation method thereof | Koyo Katsura | 2000-12-26 |
| 6108746 | Semiconductor memory having an arithmetic function and a terminal arrangement for coordinating operation with a higher processor | Ryo Fujita, Mitsuru Soga | 2000-08-22 |
| 6084599 | Graphics drawing device with hidden surface processing | Keisuke Nakashima, Shigeru Matsuo, Masahisa Narita, Koyo Katsura, Hidehito Takewa +1 more | 2000-07-04 |
| 6043820 | Perspective projection calculation devices and methods | Ichiro Iimura, Jun Satoh, Takashi Sone | 2000-03-28 |
| 5974560 | Information processor and information processing system utilizing clock signal | Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka +3 more | 1999-10-26 |
| 5968160 | Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory | Masahiko Saito, Kenichi Kurosawa, Yoshiki Kobayashi, Tadaaki Bandoh, Masahiro Iwamura +3 more | 1999-10-19 |
| 5784630 | Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory | Masahiko Saito, Kenichi Kurosawa, Yoshiki Kobayashi, Tadaaki Bandoh, Masahiro Iwamura +3 more | 1998-07-21 |
| 5748202 | Image data processor for processing pixel data in block buffer | Keisuke Nakashima, Shigeru Matsuo, Masahisa Narita, Koyo Katsura, Hidehito Takewa +1 more | 1998-05-05 |
| 5680637 | Computer having a parallel operating capability | Takashi Hotta, Shigeya Tanaka, Hiromichi Yamada, Hideo Maejima | 1997-10-21 |
| 5640547 | Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices | Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka +3 more | 1997-06-17 |
| 5561775 | Parallel processing apparatus and method capable of processing plural instructions in parallel or successively | Kenichi Kurosawa, Shigeya Tanaka, Tadaaki Bandoh | 1996-10-01 |
| 5542083 | Information processor and information processing system utilizing clock signal | Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka +3 more | 1996-07-30 |
| 5526509 | Method and apparatus for controlling one or more hierarchical memories using a virtual storage scheme and physical to virtual address translation | Toshio Doi, Takeshi Takemoto | 1996-06-11 |
| 5506982 | Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices | Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka +3 more | 1996-04-09 |
| 5404472 | Parallel processing apparatus and method capable of switching parallel and successive processing modes | Kenichi Kurosawa, Shigeya Tanaka, Tadaaki Bandoh | 1995-04-04 |
| 5392416 | Method and apparatus for controlling one or more hierarchical memories using a virtual storage scheme and physical to virtual address translation | Toshio Doi, Takeshi Takemoto | 1995-02-21 |
| 5388249 | Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices | Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka +3 more | 1995-02-07 |