Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5657242 | Method of determining routes for a plurality of wiring connections and a circuit board produced by such a method | Yutaka Sekiyama, Yasuyuki FUJIHARA, Hiromi Tanaka, Jiro Kusuhara | 1997-08-12 |
| 5329532 | Logic circuit with additional circuit for carrying out delay test | Mitsuji Ikeda, Kazumi Hatayama | 1994-07-12 |
| 5200908 | Placement optimizing method/apparatus and apparatus for designing semiconductor devices | Hiroshi Date | 1993-04-06 |
| 5144563 | Method and apparatus for optimizing element placement and method and apparatus for deciding the optimal element placement | Hiroshi Date | 1992-09-01 |
| 4960724 | Method for deleting unused gates and method for manufacturing master-slice semiconductor integrated circuit device using the deleting method | Shoichi Watanabe, Takayuki TAKEI, Takashi Natabe | 1990-10-02 |
| 4956818 | Memory incorporating logic LSI and method for testing the same LSI | Kazumi Hatayama | 1990-09-11 |
| 4710930 | Method and apparatus for diagnosing a LSI chip | Kazumi Hatayama | 1987-12-01 |
| 4701922 | Integrated circuit device | Shigeo Kuboki, Ikuro Masuda, Toshiaki Masuda | 1987-10-20 |
| 4613970 | Integrated circuit device and method of diagnosing the same | Ikuro Masuda, Hideo Maejima, Kazumi Hatayama | 1986-09-23 |