Issued Patents All Time
Showing 51–69 of 69 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5365113 | Semiconductor device | Toshiyuki Sakuta, Satoshi Oguchi, Aizo Kaneda, Masao Mitani, Shozo Nakamura +2 more | 1994-11-15 |
| 5331596 | Address multiplexed dynamic RAM having a test mode capability | Katsuhiro Shimohigashi, Jun Etoh, Katsutaka Kimura | 1994-07-19 |
| 5304868 | Non-inverting buffer circuit device and semiconductor memory circuit device | Yuji Yokoyama, Hitoshi Miwa, Shoji Wada | 1994-04-19 |
| 5287000 | Resin-encapsulated semiconductor memory device useful for single in-line packages | Yasushi Takahashi, Hidetoshi Iwai, Masaya Muranaka, Yoshitaka Kinoshita, Satoru Koshiba | 1994-02-15 |
| 5276346 | Semiconductor integrated circuit device having protective/output elements and internal circuits | Hidetoshi Iwai, Kazumichi Mitsusada, Masamichi Ishihara, Tetsuro Matsumoto, Hisao Katto +1 more | 1994-01-04 |
| 5217917 | Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor | Yasushi Takahashi, Hidetoshi Iwai, Satoshi Oguchi, Hisashi Nakamura, Hiroyuki Uchiyama +10 more | 1993-06-08 |
| 5208782 | Semiconductor integrated circuit device having a plurality of memory blocks and a lead on chip (LOC) arrangement | Toshiyuki Sakuta, Masamichi Ishihara, Masanori Tazunoki, Hidetoshi Iwai, Hisashi Nakamura +10 more | 1993-05-04 |
| 5184208 | Semiconductor device | Toshiyuki Sakuta, Satoshi Oguchi, Aizo Kaneda, Masao Mitani, Shozo Nakamura +2 more | 1993-02-02 |
| 5151772 | Semiconductor integrated circuit device | Yasushi Takahashi, Hiromi Matsuura, Yoshihisa Koyama, Masaya Muranaka, Katsutaka Kimura +2 more | 1992-09-29 |
| 5117393 | Method of testing memory cells in an address multiplexed dynamic RAM including test mode selection | Katsuhiro Shimohigashi, Jun Etoh, Katsutaka Kimura | 1992-05-26 |
| 5047983 | Semiconductor storage device with redundancy arrangement | Hidetoshi Iwai | 1991-09-10 |
| 4992985 | Method for selectively initiating/terminating a test mode in an address multiplexed DRAM and address multiplexed DRAM having such a capability | Katsuhiro Shimohigashi, Jun Etoh, Katsutaka Kimura | 1991-02-12 |
| 4943949 | Semiconductor memory including means for noise suppression | Yasunori Yamaguchi, Kanji Oishi | 1990-07-24 |
| 4934820 | Semiconductor device | Yasushi Takahashi, Hidetoshi Iwai, Masaya Muranaka | 1990-06-19 |
| 4916700 | Semiconductor storage device | Kazuya Ito, Katsutaka Kimura | 1990-04-10 |
| 4893157 | Semiconductor device | Yasunori Yamaguchi, Hiroshi Kawamoto | 1990-01-09 |
| 4873672 | Dynamic random access memory capable of fast erasing of storage data | Jun Etoh, Katsuhiro Shimohigashi, Katsutaka Kimura, Takesada Akiba | 1989-10-10 |
| 4811299 | Dynamic RAM device having a separate test mode capability | Katsuhiro Shimohigashi, Jun Etoh, Katsutaka Kimura | 1989-03-07 |
| 4562555 | Semiconductor memory device | Yoshiaki Ouchi, Masamichi Ishihara, Tetsuro Matsumoto | 1985-12-31 |