Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6748507 | Single-chip microcomputer with integral clock generating unit providing clock signals to CPU, internal circuit modules and synchronously controlling external dynamic memory | Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga +3 more | 2004-06-08 |
| 6735683 | Single-chip microcomputer with hierarchical internal bus structure having data and address signal lines coupling CPU with other processing elements | Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga +3 more | 2004-05-11 |
| 6591294 | Processing system with microcomputers each operable in master and slave modes using configurable bus access control terminals and bus use priority signals | Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga +3 more | 2003-07-08 |
| 6279063 | Microcomputer system with at least first and second microcomputers each operable in master and slave modes with configurable bus access control terminals and bus use priority controller | Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga +3 more | 2001-08-21 |
| 6223265 | Single-chip microcomputer synchronously controlling external synchronous memory responsive to memory clock signal and clock enable signal | Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga +3 more | 2001-04-24 |
| 6212620 | Single-chip microcomputer operable in master and slave modes and having configurable bus control terminals | Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga +3 more | 2001-04-03 |
| 5930523 | Microcomputer having multiple bus structure coupling CPU to other processing elements | Shumpei Kawasaki, Yasushi Akao, Kouki Noguchi, Atsushi Hasegawa, Hiroshi Ohsuga +3 more | 1999-07-27 |