Issued Patents All Time
Showing 76–100 of 101 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7310762 | Detection of errors | — | 2007-12-18 |
| 7178015 | Security measures in a partitionable computing system | Mark Shaw, Vipul Gandhi, Leon Hong, Gary Gostin, Craig Warner +9 more | 2007-02-13 |
| 6857036 | Hardware method for implementing atomic semaphore operations using code macros | — | 2005-02-15 |
| 6643766 | Speculative pre-fetching additional line on cache miss if no request pending in out-of-order processor | David Johnson | 2003-11-04 |
| 6542965 | Cache line replacement using cable status to bias way selection | — | 2003-04-01 |
| 6408363 | Speculative pre-flush of data in an out-of-order execution processor system | David Johnson | 2002-06-18 |
| 6405287 | Cache line replacement using cache status to bias way selection | — | 2002-06-11 |
| 6131156 | Optimized storage system and method for a processor that executes instructions out of order | Doug Quarnstrom, Ashok Kumar | 2000-10-10 |
| 6003107 | Circuitry for providing external access to signals that are internal to an integrated circuit chip package | Gregory L. Ranson, John W. Bockhaus, Patrick Knebel, Paul L. Perez | 1999-12-14 |
| 5956477 | Method for processing information in a microprocessor to facilitate debug and performance monitoring | Gregory L. Ranson, Russell C. Brockmann, Douglas Benson Hunt, Steven T. Mangelsdorf | 1999-09-21 |
| 5880671 | Flexible circuitry and method for detecting signal patterns on a bus | Gregory L. Ranson, John W. Bockhaus | 1999-03-09 |
| 5881224 | Apparatus and method for tracking events in a microprocessor that can retire more than one instruction during a clock cycle | Gregory L. Ranson, Russell C. Brockmann | 1999-03-09 |
| 5875340 | Optimized storage system and method for a processor that executes instructions out of order | Doug Quarnstrom, Ashok Kumar | 1999-02-23 |
| 5867644 | System and method for on-chip debug support and performance monitoring in a microprocessor | Gregory L. Ranson, John W. Bockhaus, Russell C. Brockmann, Robert E. Naas, Jonathan Lotz +4 more | 1999-02-02 |
| 5838944 | System for storing processor register data after a mispredicted branch | Donald Kipp, Samuel D. Naffziger, Jonathan Lotz | 1998-11-17 |
| 5838942 | Panic trap system and method | — | 1998-11-17 |
| 5809275 | Store-to-load hazard resolution system and method for a processor that executes instructions out of order | — | 1998-09-15 |
| 5799167 | Instruction nullification system and method for a processor that executes instructions out of order | — | 1998-08-25 |
| 5796997 | Fast nullify system and method for transforming a nullify function into a select function | Jonathan Lotz | 1998-08-18 |
| 5796975 | Operand dependency tracking system and method for a processor that executes instructions out of order | Donald Kipp | 1998-08-18 |
| 5784587 | Method and system for recovering from cache misses | Jonathan Lotz, Donald Kipp | 1998-07-21 |
| 5761713 | Address aggregation system and method for increasing throughput to a multi-banked data cache from a processor by concurrently forwarding an address to each bank | — | 1998-06-02 |
| 5761474 | Operand dependency tracking system and method for a processor that executes instructions out of order | Ashok Kumar | 1998-06-02 |
| 5758178 | Miss tracking system and method | — | 1998-05-26 |
| 5748934 | Operand dependency tracking system and method for a processor that executes instructions out of order and that permits multiple precision data words | Doug Quarnstrom, Jonathan Lotz | 1998-05-05 |