Issued Patents All Time
Showing 26–47 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10491545 | Virtual channel routing | Nicholas George McDonald, Gary Gostin, Darel N. Emmot, Gregg B. Lesartre, Al Davis | 2019-11-26 |
| 10489298 | Hardware flush assist | Shawn Walker | 2019-11-26 |
| 10437500 | Committing altered metadata to a non-volatile storage device | Gregg B. Lesartre | 2019-10-08 |
| 10409681 | Non-idempotent primitives in fault-tolerant memory | Harvey Ray | 2019-09-10 |
| 10402287 | Preventing data corruption and single point of failure in a fault-tolerant memory | Harvey Ray, Chris Michael Brueggen | 2019-09-03 |
| 10402261 | Preventing data corruption and single point of failure in fault-tolerant memory fabrics | Harvey Ray | 2019-09-03 |
| 10402113 | Live migration of data | Harvey Ray, Gregg B. Lesartre | 2019-09-03 |
| 10394635 | CPU with external fault response handling | — | 2019-08-27 |
| 10355978 | Calculating times to live for transaction requests | Gregg B. Lesartre, Gary Gostin, Nicholas George McDonald, Alan L. Davis, Darel N. Emmot +1 more | 2019-07-16 |
| 10338965 | Managing a set of resources | Christopher Michael Brueggen, Harvey Ray | 2019-07-02 |
| 10228884 | Issuing write requests to a fabric | Shawn Walker | 2019-03-12 |
| 10069745 | Lossy fabric transmitting device | Gary Gostin | 2018-09-04 |
| 9946656 | Completion packet return based on eviction or flush | Gregg B. Lesartre | 2018-04-17 |
| 9929899 | Snapshot message | Michael Kontz | 2018-03-27 |
| 9148384 | Posted and unencumbered queues | — | 2015-09-29 |
| 8880760 | Self organizing heap method includes a packet reordering method based on packet passing rules only reordering packets from a load/unload input signal is asserted | Matthew Lovell | 2014-11-04 |
| 8281176 | Buffer circuit and method | — | 2012-10-02 |
| 7610526 | On-chip circuitry for bus validation | Jayen Desai, Chih-Jen Chen | 2009-10-27 |
| 7447971 | Data recovery systems and methods | — | 2008-11-04 |
| 6304936 | One-to-many bus bridge using independently and simultaneously selectable logical FIFOS | — | 2001-10-16 |
| 6269413 | System with multiple dynamically-sized logical FIFOs sharing single memory and with read/write pointers independently selectable and simultaneously responsive to respective read/write FIFO selections | — | 2001-07-31 |
| 6157977 | Bus bridge and method for ordering read and write operations in a write posting system | Thomas Spencer, IV, Francisco Corella | 2000-12-05 |