Issued Patents All Time
Showing 26–29 of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5619647 | System for multiplexing prioritized virtual channels onto physical channels where higher priority virtual will pre-empt a lower priority virtual or a lower priority will wait | — | 1997-04-08 |
| 5075844 | Paired instruction processor precise exception handling mechanism | Shannon J. Lynch, Philip Manela, Robert W. Horst | 1991-12-24 |
| 5072364 | Method and apparatus for recovering from an incorrect branch prediction in a processor that executes a family of instructions in parallel | Shannon J. Lynch, Philip Manela, Robert W. Horst | 1991-12-10 |
| 5016208 | Deferred comparison multiplier checker | Robert W. Horst | 1991-05-14 |