SS

Satoru Sueki

HT Headway Technologies: 12 patents #72 of 309Top 25%
Tdk: 12 patents #488 of 3,796Top 15%
S( Sae Magnetics (H.K.): 5 patents #87 of 585Top 15%
Overall (All Time): #422,702 of 4,157,543Top 15%
12
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
8513034 Method of manufacturing layered chip package Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Hiroshi Ikejima 2013-08-20
8324741 Layered chip package with wiring on the side surfaces Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Hiroshi Ikejima 2012-12-04
8154116 Layered chip package with heat sink Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Hiroshi Ikejima 2012-04-10
8134229 Layered chip package Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa 2012-03-13
7968374 Layered chip package with wiring on the side surfaces Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Hiroshi Ikejima 2011-06-28
7964976 Layered chip package and method of manufacturing same Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Hiroshi Ikejima 2011-06-21
7868442 Layered chip package and method of manufacturing same Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa 2011-01-11
7863095 Method of manufacturing layered chip package Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa 2011-01-04
7846772 Layered chip package and method of manufacturing same Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa 2010-12-07
7767494 Method of manufacturing layered chip package Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa 2010-08-03
7745259 Layered chip package and method of manufacturing same Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa 2010-06-29
7557439 Layered chip package that implements memory device Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Ryuji Hashimoto 2009-07-07