HI

Hiroshi Ikejima

HT Headway Technologies: 24 patents #47 of 309Top 20%
S( Sae Magnetics (H.K.): 24 patents #20 of 585Top 4%
Tdk: 5 patents #1,099 of 3,796Top 30%
Overall (All Time): #174,672 of 4,157,543Top 5%
24
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
8652877 Method of manufacturing layered chip package Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima 2014-02-18
8653639 Layered chip package and method of manufacturing same Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima 2014-02-18
8618646 Layered chip package and method of manufacturing same Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima 2013-12-31
8541887 Layered chip package and method of manufacturing same Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima 2013-09-24
8513034 Method of manufacturing layered chip package Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki 2013-08-20
8466562 Layered chip package Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima 2013-06-18
8462482 Ceramic capacitor and method of manufacturing same Yoshitaka Sasaki, Atsushi Iijima 2013-06-11
8441112 Method of manufacturing layered chip package Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima 2013-05-14
8432662 Ceramic capacitor and method of manufacturing same Yoshitaka Sasaki, Atsushi Iijima 2013-04-30
8426979 Composite layered chip package Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima 2013-04-23
8421243 Layered chip package and method of manufacturing same Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima 2013-04-16
8362602 Layered chip package and method of manufacturing same Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima 2013-01-29
8358015 Layered chip package and method of manufacturing same Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima 2013-01-22
8344494 Layered chip package and method of manufacturing same Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima 2013-01-01
8324741 Layered chip package with wiring on the side surfaces Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki 2012-12-04
8253257 Layered chip package and method of manufacturing the same Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima 2012-08-28
8203215 Layered chip package and method of manufacturing same Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima 2012-06-19
8203216 Layered chip package and method of manufacturing same Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima 2012-06-19
8171607 Method of manufacturing ceramic capacitor Yoshitaka Sasaki, Atsushi Iijima 2012-05-08
8154116 Layered chip package with heat sink Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki 2012-04-10
7968374 Layered chip package with wiring on the side surfaces Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki 2011-06-28
7964976 Layered chip package and method of manufacturing same Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki 2011-06-21
7915083 Method of manufacturing layered chip package Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima 2011-03-29
7902677 Composite layered chip package and method of manufacturing same Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima 2011-03-08