Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8606974 | Direct memory access controller | Koji Takenouchi | 2013-12-10 |
| 7716390 | Direct memory access controller | Koji Takenouchi | 2010-05-11 |
| 7634593 | System and method for DMA transfer | — | 2009-12-15 |
| 7434079 | Microcomputer, method of controlling cache memory, and method of controlling clock | — | 2008-10-07 |
| 7162563 | Semiconductor integrated circuit having changeable bus width of external data signal | Satoshi Matsui | 2007-01-09 |
| 7012454 | Clock shift circuit for gradual frequency change | Satoshi Matsui, Yukihiro Ozawa | 2006-03-14 |
| 7007134 | Microcomputer, method of controlling cache memory, and method of controlling clock | — | 2006-02-28 |
| 6880066 | Central processing unit and system having a prefetch queue and a command cache to perform an efficient information reading operation | — | 2005-04-12 |
| 6708266 | Central processing unit and system counting instructions in a queue storage and outputting a fetch request when the count value is 0 or 1 to produce a next instruction address output | — | 2004-03-16 |
| 6535960 | Partitioned cache memory with switchable access paths | Syuji Nishida, Shunsuke Kamijo, Kenji Furuya | 2003-03-18 |
| 5822557 | Pipelined data processing device having improved hardware control over an arithmetic operations unit | Koichi Hatta, Hideyuki Iino, Tatsuya Nagasawa | 1998-10-13 |
| 5822762 | Information processing device with decision circuits and partitioned address areas | Syuji Nishida, Shunsuke Kamijo, Kenji Furuya | 1998-10-13 |
| 5742839 | Coprocessor for performing an arithmetic operation by automatically reading data from an external memory | Koichi Hatta, Hideyuki Iino, Tatsuya Nagasawa | 1998-04-21 |
| 5742842 | Data processing apparatus for executing a vector operation under control of a master processor | Hideyuki Iino, Koichi Hatta, Tatsuya Nagasawa, Koichi Kuroiwa, Hiroyuki Fujiyama +4 more | 1998-04-21 |