Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6877112 | Reset control system and method | Hiroyuki Utsumi, Yoshio Hirose, Ken Ryu | 2005-04-05 |
| 5822557 | Pipelined data processing device having improved hardware control over an arithmetic operations unit | Seiji Suetake, Koichi Hatta, Tatsuya Nagasawa | 1998-10-13 |
| 5809552 | Data processing system, memory access device and method including selecting the number of pipeline stages based on pipeline conditions | Koichi Kuroiwa, Hiroyuki Fujiyama, Kenji Shirasawa, Masaharu Kimura, Noriko Kadomaru +2 more | 1998-09-15 |
| 5768559 | Multiple bank structured memory access device having flexible setting of a pipeline stage number | Hiromasa Takahashi | 1998-06-16 |
| 5742842 | Data processing apparatus for executing a vector operation under control of a master processor | Seiji Suetake, Koichi Hatta, Tatsuya Nagasawa, Koichi Kuroiwa, Hiroyuki Fujiyama +4 more | 1998-04-21 |
| 5742839 | Coprocessor for performing an arithmetic operation by automatically reading data from an external memory | Seiji Suetake, Koichi Hatta, Tatsuya Nagasawa | 1998-04-21 |
| 5724548 | System including processor and cache memory and method of controlling the cache memory | Hiromasa Takahashi | 1998-03-03 |
| 5699553 | Memory accessing device for a pipeline information processing system | Hiromasa Takahashi, Hiroyuki Fujiyama, Koichi Kuroiwa, Kenji Shirasawa | 1997-12-16 |
| 5654972 | Processor having test circuit | Koichi Kuroiwa | 1997-08-05 |
| 5644748 | Processor system including an index buffer circuit and a translation look-aside buffer control circuit for processor-to-processor interfacing | Shinichi Utsunomiya, Noriko Kadomaru, Makoto Miyagawa | 1997-07-01 |
| 5586282 | Memory system employing pipeline process for accessing memory banks | Hiromasa Takahashi | 1996-12-17 |
| 5551010 | Arithmetic operation unit and memory accessing device for accessing primary and secondary cache memories independently of a CPU | Hiromasa Takahashi | 1996-08-27 |
| 5526494 | Bus controller | Hiromasa Takahashi | 1996-06-11 |
| 5056011 | Direct memory access controller with expedited error control | Akihiro Yoshitake, Hidenori Hida | 1991-10-08 |
| 4929854 | Clock circuit having a clocked output buffer | Akihiro Yoshitake, Hidenori Hida | 1990-05-29 |
| 4904883 | Semiconductor integrated circuit having a DC test function | Hidenori Hida | 1990-02-27 |