Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8588743 | Communication device and communication system | Hiroyoshi Yamashita | 2013-11-19 |
| 6839811 | Semaphore management circuit | — | 2005-01-04 |
| 6292861 | Processor having interface with bus arbitration circuit | — | 2001-09-18 |
| 6078202 | Semiconductor device having portions that operate at different frequencies, and method of designing the device | Hideaki Tomatsuri, Noriaki Ono, Minoru Usui | 2000-06-20 |
| 6009493 | Data transfer control method and apparatus for performing consecutive burst transfer operations with a simple structure | — | 1999-12-28 |
| 5809552 | Data processing system, memory access device and method including selecting the number of pipeline stages based on pipeline conditions | Koichi Kuroiwa, Hideyuki Iino, Kenji Shirasawa, Masaharu Kimura, Noriko Kadomaru +2 more | 1998-09-15 |
| 5742842 | Data processing apparatus for executing a vector operation under control of a master processor | Seiji Suetake, Hideyuki Iino, Koichi Hatta, Tatsuya Nagasawa, Koichi Kuroiwa +4 more | 1998-04-21 |
| 5699553 | Memory accessing device for a pipeline information processing system | Hideyuki Iino, Hiromasa Takahashi, Koichi Kuroiwa, Kenji Shirasawa | 1997-12-16 |
| 5146595 | Grouping device for forming input signals into groups | Kouichi Kuroiwa, Shinji Nishikawa, Hidetoshi Shimura, Shinji Oyamada | 1992-09-08 |
| 5119496 | Method and apparatus for interrupt processing in a computer system having peripheral units connected in a daisy chain | Sinji Nishikawa, Kouichi Kuroiwa, Shinji Oyamada, Hidetoshi Shimura | 1992-06-02 |
| 4866742 | Register circuit with plural registers simultaneously reset when a selected register receives data | Sinji Nishikawa | 1989-09-12 |