Issued Patents All Time
Showing 76–100 of 102 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8108392 | Identifying clusters of words according to word affinities | David L. Marvit, Stergios Stergiou, Alex Gilman, B. Thomas Adler, John J. Sidorowich | 2012-01-31 |
| 8060503 | Ranking nodes for session-based queries | Stergios Stergiou | 2011-11-15 |
| 8041665 | Compact decision diagrams | Stergios Stergiou | 2011-10-18 |
| 7788556 | System and method for evaluating an erroneous state associated with a target circuit | Subramanian K. Iyer, Amit Narayan, Debashis Sahoo | 2010-08-31 |
| 7673263 | Method for verifying and representing hardware by decomposition and partitioning | — | 2010-03-02 |
| 7594195 | Multithreaded reachability | Debashis Sahoo | 2009-09-22 |
| 7571403 | Circuit verification | Subramanian K. Iyer, Amit Narayan, Debashis Sahoo, Christian Stangier | 2009-08-04 |
| 7546563 | Validating one or more circuits using one of more grids | Subramanian K. Iyer, Mukul R. Prasad, Thomas W. Sidle | 2009-06-09 |
| 7451375 | Directed falsification of a circuit | — | 2008-11-11 |
| 7280993 | Reachability-based verification of a circuit using one or more multiply rooted binary decision diagrams | — | 2007-10-09 |
| 7281225 | Circuit verification using multiple engines | Koichiro Takayama, Debashis Sahoo | 2007-10-09 |
| 7216312 | Determining one or more reachable states in a circuit using distributed computing and one or more partitioned data structures | Amit Narayan, Yoshihisa Kojima, Takaya Ogawa, Subramanian K. Iyer, Debashis Sahoo | 2007-05-08 |
| 7076712 | Generating a test sequence using a satisfiability technique | Mukul R. Prasad, Michael Hsiao | 2006-07-11 |
| 7065722 | System and method for building a binary decision diagram associated with a target circuit | — | 2006-06-20 |
| 7032192 | Performing latch mapping of sequential circuits | Mukul R. Prasad, Rajarshi Mukherjee, Kelvin Kwok-Cheung Ng | 2006-04-18 |
| 7032197 | System and method for executing image computation associated with a target circuit | Subramanian K. Iyer, Amit Narayan, Debashis Sahoo, Christian Stangier | 2006-04-18 |
| 7028279 | Circuit verification | Subramanian K. Iyer, Amit Narayan, Debashis Sahoo, Christian Stangier | 2006-04-11 |
| 7028278 | Method of verifying and representing hardware by decomposition and partitioning | — | 2006-04-11 |
| 6904578 | System and method for verifying a plurality of states associated with a target circuit | Amit Narayan, Subramanian K. Iyer, Debashis Sahoo | 2005-06-07 |
| 6560758 | Method for verifying and representing hardware by decomposition and partitioning | — | 2003-05-06 |
| 6532440 | Multiple error and fault diagnosis based on Xlists | Vamsi Boppana, Rajarshi Mukherjee, Masahiro Fujita | 2003-03-11 |
| 6408424 | Verification of sequential circuits with same state encoding | Rajarshi Mukherjee, Vamsi Boppana | 2002-06-18 |
| 6389374 | OBDD variable ordering using sampling based schemes | Yuan Lu | 2002-05-14 |
| 6301687 | Method for verification of combinational circuits using a filtering oriented approach | Rajarshi Mukherjee, Koichiro Takayama | 2001-10-09 |
| 6212669 | Method for verifying and representing hardware by decomposition and partitioning | — | 2001-04-03 |