Issued Patents All Time
Showing 276–300 of 302 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5416910 | Method and apparatus for performing bus arbitration in a data processing system | James B. Gullette, Michael Garcia | 1995-05-16 |
| 5388226 | Method and apparatus for accessing a register in a data processing system | Joseph Gutierrez, Yui K. Ho, Pee-Keong Or | 1995-02-07 |
| 5375216 | Apparatus and method for optimizing performance of a cache memory in a data processing system | John Arends, Christopher E. White, Keith E. Diefendorff | 1994-12-20 |
| 5347523 | Data processing system having serial self address decoding and method of operation | Sunil Khatri, William C. Bruce, Jr. | 1994-09-13 |
| 5341500 | Data processor with combined static and dynamic masking of operand for breakpoint operation | Joseph Gutierrez, Yui K. Ho | 1994-08-23 |
| 5319763 | Data processor with concurrent static and dynamic masking of operand information and method therefor | Yui K. Ho, Joseph Gutierrez | 1994-06-07 |
| 5239642 | Data processor with shared control and drive circuitry for both breakpoint and content addressable storage devices | Joseph Gutierrez, Yui K. Ho | 1993-08-24 |
| 5029072 | Lock warning mechanism for a cache | Ralph McGarity, James G. Gay, Jesse R. Wilson | 1991-07-02 |
| 4914573 | Bus master which selectively attempts to fill complete entries in a cache line | Hunter Ledbetter Scales, III, Donald C. Anderson | 1990-04-03 |
| 4910656 | Bus master having selective burst initiation | Hunter Ledbetter Scales, III, William D. Wilson | 1990-03-20 |
| 4890223 | Paged memory management unit which evaluates access permissions when creating translator | Michael Cruess, John Zolnowsky | 1989-12-26 |
| 4888688 | Dynamic disable mechanism for a memory management unit | Jay A. Hartvigsen | 1989-12-19 |
| 4887203 | Microcoded processor executing microroutines with a user specified starting microaddress | Douglas B. MacGregor, John Zolnowsky, David S. Mothersole | 1989-12-12 |
| 4862352 | Data processor having pulse width encoded status output signal | Jay A. Hartvigsen, Russell Stanphill | 1989-08-29 |
| 4816997 | Bus master having selective burst deferral | Hunter Ledbetter Scales, III, William D. Wilson | 1989-03-28 |
| 4802086 | FINUFO cache replacement method and apparatus | James G. Gay, Jesse R. Wilson, Terry V. Hulett | 1989-01-31 |
| 4800489 | Paged memory management unit capable of selectively supporting multiple address spaces | Michael Cruess, William M. Keshlear, John Zolnowsky | 1989-01-24 |
| 4799199 | Bus master having burst transfer mode | Hunter Ledbetter Scales, III, William D. Wilson | 1989-01-17 |
| 4763244 | Paged memory management unit capable of selectively supporting multiple address spaces | Michael Cruess, William M. Keshlear, John Zolnowsky | 1988-08-09 |
| 4763250 | Paged memory management unit having variable number of translation table levels | William M. Keshlear, John Zolnowsky | 1988-08-09 |
| 4729094 | Method and apparatus for coordinating execution of an instruction by a coprocessor | John Zolnowsky, David S. Mothersole, Douglas B. MacGregor | 1988-03-01 |
| 4649477 | Operand size mechanism for control simplification | Douglas B. MacGregor | 1987-03-10 |
| 4635193 | Data processor having selective breakpoint capability with minimal overhead | John Zolnowsky, David S. Mothersole | 1987-01-06 |
| 4580213 | Microprocessor capable of automatically performing multiple bus cycles | Terry V. Hulett, Bradly A. Setering, Michael E. Spak | 1986-04-01 |
| 4524415 | Virtual machine data processor | Marvin A. Mills, Jr., Douglas B. MacGregor, John Zolnowsky | 1985-06-18 |