Issued Patents All Time
Showing 51–75 of 101 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10666262 | Programmable array logic | — | 2020-05-26 |
| 10666141 | Control device and power conversion circuit thereof with reconfigurable power structure | — | 2020-05-26 |
| 10587271 | Clock distribution and generation architecture for logic tiles of an integrated circuit and method of operating same | Nitish U. Natu | 2020-03-10 |
| 10587269 | Integrated circuit including an array of logic tiles, each logic tile including a configurable switch interconnect network | — | 2020-03-10 |
| 10566781 | Input/output buffer circuit with a protection circuit | Chai-Teck Gan | 2020-02-18 |
| 10551862 | System on chip with different current setting modes | — | 2020-02-04 |
| 10523209 | Test circuitry and techniques for logic tiles of FPGA | — | 2019-12-31 |
| 10429206 | Counting device and pedometer device | Hsi-Jung Tsai, Chih-Wei Tsai | 2019-10-01 |
| 10432196 | Communication device, communication system and operation method thereof | — | 2019-10-01 |
| 10411711 | FPGA having a virtual array of logic tiles, and method of configuring and operating same | Anthony Kozaczuk, Abhijit M. Abhyankar | 2019-09-10 |
| 10411712 | FPGA having programmable powered-up/powered-down logic tiles, and method of configuring and operating same | Anthony Kozaczuk, Valentin Ossman | 2019-09-10 |
| 10348307 | Clock distribution and generation architecture for logic tiles of an integrated circuit and method of operating same | Nitish U. Natu | 2019-07-09 |
| 10348308 | Clock architecture, including clock mesh fabric, for FPGA, and method of operating same | Nitish U. Natu, Abhijit M. Abhyankar | 2019-07-09 |
| 10275017 | Power circuit and memory device using the same | Hsi-Jung Tsai | 2019-04-30 |
| 10250262 | Integrated circuit including an array of logic tiles, each logic tile including a configurable switch interconnect network | — | 2019-04-02 |
| 10237066 | Multi-channel encryption and authentication | Martin Langhammer, Shawn David Nicholl | 2019-03-19 |
| 10176865 | Programmable decoupling capacitance of configurable logic circuitry and method of operating same | — | 2019-01-08 |
| 10094689 | Fluid flow metering device and method thereof | Hsi-Jung Tsai, Jing-Shiang Tseng, Chia-Ching Lu | 2018-10-09 |
| 10073555 | Sensing device | — | 2018-09-11 |
| 9984750 | Non-volatile memory device and operating method thereof | — | 2018-05-29 |
| 9973194 | Block memory layout and architecture for programmable logic IC, and method of operating same | Geoffrey R. Tate | 2018-05-15 |
| 9941887 | Multiplexer-memory cell circuit, layout thereof and method of manufacturing same | — | 2018-04-10 |
| 9906225 | Integrated circuit including an array of logic tiles, each logic tile including a configurable switch interconnect network | — | 2018-02-27 |
| 9898123 | Sensing device | Chih-Ping Lu | 2018-02-20 |
| 9882568 | Clock distribution architecture for logic tiles of an integrated circuit and method of operation thereof | — | 2018-01-30 |