Yan Solihin — 57 Patents at Empire Technology Development

Yan Solihin has been granted 57 US patents while listed as an inventor at Empire Technology Development. The first was granted in 2012 and the most recent in March 2022. Yan Solihin ranks #42,642 of 4,157,543 US inventors in our database (top 1.0%). Patent records list Yan Solihin in Raleigh, NC, US.

Issued Patents All Time

Showing 1–25 of 57 patents

Patent #	Title	Co-Inventors	Date
11281545	Methods of crash recovery for data stored in non-volatile main memory	Mohammad Alshboul, James Tuck	2022-03-22
10956331	Cache partitioning in a multicore processor	—	2021-03-23
10445131	Core prioritization for heterogeneous on-chip networks	—	2019-10-15
10445287	Circuit switch pre-reservation in an on-chip network	—	2019-10-15
10346308	Cache partitioning in a multicore processor	—	2019-07-09
10346227	Increased refresh interval and energy efficiency in a DRAM	—	2019-07-09
10289452	Thread and data assignment in multi-core processors based on cache miss data and thread category	—	2019-05-14
10176107	Methods and systems for dynamic DRAM cache sizing	—	2019-01-08
10152410	Magnetoresistive random-access memory cache write management	—	2018-12-11
10007605	Hardware-based array compression	—	2018-06-26
9990293	Energy-efficient dynamic dram cache sizing via selective refresh of a cache in a dram	—	2018-06-05
9965385	Memory allocation accelerator	—	2018-05-08
9946647	Directory coherence for multicore processors	—	2018-04-17
9916255	Data storage based on memory persistency	—	2018-03-13
9858111	Heterogeneous magnetic memory architecture	—	2018-01-02
9846627	Systems and methods for modeling memory access behavior and memory traffic timing behavior	Yipeng Wang, Amro Awad	2017-12-19
9772950	Multi-granular cache coherence	—	2017-09-26
9766681	Operations related to a retransmission buffer	Ahmad Samih	2017-09-19
9760486	Accelerating cache state transfer on a directory-based multicore architecture	—	2017-09-12
9710303	Shared cache data movement in thread migration	—	2017-07-18
9684603	Memory initialization using cache state	—	2017-06-20
9678550	Dynamic router power control in multi-core processors	Mazen Kharbutli	2017-06-13
9632832	Thread and data assignment in multi-core processors based on cache miss data	—	2017-04-25
9612961	Cache partitioning in a multicore processor	—	2017-04-04
9564202	Increased refresh interval and energy efficiency in a DRAM	—	2017-02-07

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Yan Solihin — 57 Patents

Issued Patents All Time

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