Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12072379 | Dynamic scan obfuscation for integrated circuit protections | Jonti Talukdar, Arjun Chaudhuri | 2024-08-27 |
| 12039091 | Integrated circuit protections against removal and oracle-guided attacks | Jonti Talukdar | 2024-07-16 |
| 12008298 | Evaluating functional fault criticality of structural faults for circuit testing | Arjun Chaudhuri, Jonti Talukdar | 2024-06-11 |
| 11971790 | Online fault detection in ReRAM-based AI/ML | Mengyun Liu | 2024-04-30 |
| 11714129 | Observation point injection for integrated circuit testing | Arjun Chaudhuri | 2023-08-01 |
| 11568113 | Variation-aware delay fault testing | Sanmitra Banerjee | 2023-01-31 |
| 10845416 | Software-based self-test and diagnosis using on-chip memory | Sergej Deutsch | 2020-11-24 |
| 10838003 | Multi-layer integrated circuits having isolation cells for layer testing and related methods | Ran Wang | 2020-11-17 |
| 10788532 | Software-based self-test and diagnosis using on-chip memory | Sergej Deutsch | 2020-09-29 |
| 10775429 | Testing monolithic three dimensional integrated circuits | Sukeshwar Kannan, Abhishek Koneru | 2020-09-15 |
| 10732221 | Signal tracing using on-chip memory for in-system post-fabrication debug | Sergej Deutsch | 2020-08-04 |
| 10444279 | Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels | Sergej Deutsch | 2019-10-15 |
| 10338133 | Multi-layer integrated circuits having isolation cells for layer testing and related methods | Ran Wang | 2019-07-02 |
| 9864007 | Software-based self-test and diagnosis using on-chip memory | Sergej Deutsch | 2018-01-09 |
| 9720036 | Signal tracing using on-chip memory for in-system post-fabrication debug | Sergej Deutsch | 2017-08-01 |
| 9482720 | Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels | Sergej Deutsch | 2016-11-01 |
| 9367268 | Print production scheduling | Jun Zeng, Qing Duan, I-Jong Lin, Gary J. Dispoto | 2016-06-14 |
| 9201042 | Architectural layout for dilution with reduced wastage in digital microfluidic based lab-on-a-chip | Bhargab B. Bhattacharya, Sudip Roy | 2015-12-01 |
| 9128014 | High throughput and volumetric error resilient dilution with digital microfluidic based lab-on-a-chip | Bhargab B. Bhattacharya, Sarmishtha Ghoshal, Sudip Roy | 2015-09-08 |
| 8832608 | Retiming-based design flow for delay recovery on inter-die paths in 3D ICs | Brandon Noia | 2014-09-09 |
| 8782479 | Scan test of die logic in 3D ICs using TSV probing | Brandon Noia | 2014-07-15 |
| 8775108 | Method and architecture for pre-bond probing of TSVs in 3D stacked integrated circuits | Brandon Noia | 2014-07-08 |
| 8373493 | Power switch design and method for reducing leakage power in low-power integrated circuits | Chrysovalantis Kavousianos, Zhaobo Zhang | 2013-02-12 |
| 5790562 | Circuit with built-in test and method thereof | Brian Murray, John P. Hayes | 1998-08-04 |