KC

Kumar Chinnaswamy

DE Digital Equipment: 8 patents #114 of 2,100Top 6%
IN Intel: 4 patents #8,473 of 30,777Top 30%
BB Bigband Networks Bas: 1 patents #4 of 12Top 35%
Overall (All Time): #349,367 of 4,157,543Top 9%
14
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
10134471 Hybrid memory architectures Randy B. Osborne, Erik W. Peter 2018-11-20
8914568 Hybrid memory architectures Randy B. Osborne, Erik W. Peter 2014-12-16
8250573 Audio subsystem sharing in a virtualized environment Abhishek Singhal, Devon Worrell, Nitin V. Sarangdhar 2012-08-21
8219797 Method and system to facilitate configuration of a hardware device in a platform Ittai Anati, Alberto J. Martinez, Shay Gueron 2012-07-10
6826195 System and process for high-availability, direct, flexible and scalable switching of data packets in broadband networks Paul E. Nikolich, Paul Dormitzer, Willem Engelse, Walter G. Mahla, Howard Ngai +3 more 2004-11-30
6611526 System having a meshed backplane and process for transferring data therethrough Paul Dormitzer 2003-08-26
5371874 Write-read/write-pass memory subsystem cycle Michael A. Gagliardo, John J. Lynch, James E. Tessari 1994-12-06
5313623 Method and apparatus for performing diagnosis scanning of a memory unit regardless of the state of the system clock and without affecting the store data Hansel A. Collins, Michael B. Evans, Timothy P. Fissette, Michael A. Gagliardo, John J. Lynch +1 more 1994-05-17
5255381 Mode switching for a memory system with diagnostic scan Hansel A. Collins, Michael B. Evans, Timothy P. Fissette, Michael A. Gagliardo, John J. Lynch +1 more 1993-10-19
5235693 Method and apparatus for reducing buffer storage in a read-modify-write operation Michael A. Gagliardo, Paul M. Goodwin, John J. Lynch, James E. Tessari 1993-08-10
5185875 Method and apparatus for reducing memory read latency in a shared memory system with multiple processors Michael A. Gagliardo, John J. Lynch, James E. Tessari 1993-02-09
5043874 Memory configuration for use with means for interfacing a system control unit for a multi-processor system with the system main memory Michael A. Gagliardo, James E. Tessari, John J. Lynch 1991-08-27
5008886 Read-modify-write operation Michael A. Gagliardo, Paul M. Goodwin, John J. Lynch, James E. Tessari 1991-04-16
4968977 Modular crossbar interconnection metwork for data transactions between system units in a multi-processor system Michael Flynn, R. Stephen Polzin 1990-11-06