| 5408641 |
Programmable data transfer timing |
Michael A. Gagliardo, John J. Lynch |
1995-04-18 |
| 5371874 |
Write-read/write-pass memory subsystem cycle |
Kumar Chinnaswamy, Michael A. Gagliardo, John J. Lynch |
1994-12-06 |
| 5335337 |
Programmable data transfer timing |
Michael A. Gagliardo, John J. Lynch |
1994-08-02 |
| 5313623 |
Method and apparatus for performing diagnosis scanning of a memory unit regardless of the state of the system clock and without affecting the store data |
Kumar Chinnaswamy, Hansel A. Collins, Michael B. Evans, Timothy P. Fissette, Michael A. Gagliardo +1 more |
1994-05-17 |
| 5255381 |
Mode switching for a memory system with diagnostic scan |
Kumar Chinnaswamy, Hansel A. Collins, Michael B. Evans, Timothy P. Fissette, Michael A. Gagliardo +1 more |
1993-10-19 |
| 5235693 |
Method and apparatus for reducing buffer storage in a read-modify-write operation |
Kumar Chinnaswamy, Michael A. Gagliardo, Paul M. Goodwin, John J. Lynch |
1993-08-10 |
| 5185875 |
Method and apparatus for reducing memory read latency in a shared memory system with multiple processors |
Kumar Chinnaswamy, Michael A. Gagliardo, John J. Lynch |
1993-02-09 |
| 5043874 |
Memory configuration for use with means for interfacing a system control unit for a multi-processor system with the system main memory |
Michael A. Gagliardo, John J. Lynch, Kumar Chinnaswamy |
1991-08-27 |
| 5008886 |
Read-modify-write operation |
Kumar Chinnaswamy, Michael A. Gagliardo, Paul M. Goodwin, John J. Lynch |
1991-04-16 |