Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8631905 | Ladder apparatus | — | 2014-01-21 |
| 5869366 | Method for forming voltage clamp having a breakdown voltage of 40 Vdc | Edward H. Honnigford, Tracy Adam Noll | 1999-02-09 |
| 5734186 | CMOS voltage clamp | Edward H. Honnigford, Tracy Adam Noll | 1998-03-31 |
| 5366916 | Method of making a high voltage implanted channel device for VLSI and ULSI processes | Richard A. Summe, Randy A. Rusch, Douglas R. Schnabel | 1994-11-22 |
| 5047358 | Process for forming high and low voltage CMOS transistors on a single integrated circuit chip | Walter K. Kosiak, Douglas R. Schnabel, Jonathan Mann, Paul R. Rowlands, III | 1991-09-10 |
| 4918026 | Process for forming vertical bipolar transistors and high voltage CMOS in a single integrated circuit chip | Walter K. Kosiak, Douglas R. Schnabel, Jonathan Mann, Paul R. Rowlands, III | 1990-04-17 |