SR

S. Babar Raza

Cypress Semiconductor: 48 patents #8 of 1,852Top 1%
📍 Sunnyvale, CA: #351 of 14,302 inventorsTop 3%
🗺 California: #8,171 of 386,348 inventorsTop 3%
Overall (All Time): #56,851 of 4,157,543Top 2%
49
Patents All Time

Issued Patents All Time

Showing 26–49 of 49 patents

Patent #TitleCo-InventorsDate
6578118 Method and logic for storing and extracting in-band multicast port information stored along with the data in a single memory without memory read cycle overhead Somnath Paul 2003-06-10
6510487 Design architecture for a parallel and serial programming interface Anita X. Meng, Donald A. Krall, Khaldoon S. Abugharbieh, Roger Bettman 2003-01-21
6502197 Method and architecture for synchronizing a transport and path overhead generator and/or extractor to an path overhead transport and path processor 2002-12-31
6243664 Methods for maximizing routability in a programmable interconnect matrix having less than full connectability Hagop Nazarian, Stephen M. Douglass, W. Alfred Graf, Sundar Rajan, Shiva Sorooshian Borzin +1 more 2001-06-05
6229811 Architecture for a dual segment dual speed repeater M. Magdy Talaat, Yun-Che Wang, Michael J. Kasper 2001-05-08
6195360 Architecture for a dual segment dual speed repeater M. Magdy Talaat 2001-02-27
6118299 Method and apparatus to generate mask programmable device 2000-09-12
6115364 Distributed port select method for a multi-segment repeater M. Magdy Talaat 2000-09-05
6097738 Multi-speed retainer M. Magdy Talaat 2000-08-01
6055241 Architecture for a dual segment dual speed repeater M. Magdy Talaat, Yun-Che Wang, Michael J. Kasper 2000-04-25
5986489 Slew rate control circuit for an integrated circuit Lin-Shih Liu, Hagop Nazarian 1999-11-16
5973545 Single pump circuit for generating high voltage from two different inputs 1999-10-26
5943488 Method and apparatus to generate mask programmable device 1999-08-24
5926035 Method and apparatus to generate mask programmable device 1999-07-20
5923868 Methods for maximizing routability in a programmable interconnect matrix having less than full connectability Hagop Nazarian, Stephen M. Douglass, W. Alfred Graf, Sundar Rajan, Shiva Sorooshian Borzin +1 more 1999-07-13
5848066 Methods for maximizing routability in a programmable interconnect matrix having less than full connectability Hagop Nazarian, Stephen M. Douglass, W. Alfred Graf, Sundar Rajan, Shiva Sorooshian Borzin +1 more 1998-12-08
5821794 Clock distribution architecture and method for high speed CPLDs Hagop Nazarian, Donald A. Krall 1998-10-13
5748559 Circuit for high speed serial programming of programmable logic devices James B. MacArthur 1998-05-05
5745354 Pump circuit for generating multiple high voltage outputs from two different inputs 1998-04-28
5710778 High voltage reference and measurement circuit for verifying a programmable cell Roger Bettman, Donald Y. Yu, Donald A. Krall, Anita X. Meng, Christopher S. Norris 1998-01-20
5689686 Methods for maximizing routability in a programmable interconnect matrix having less than full connectability Hagop Nazarian, Stephen M. Douglass, W. Alfred Graf, Sundar Rajan, Shiva Sorooshian Borzin +1 more 1997-11-18
5654652 High-speed ratio CMOS logic structure with static and dynamic pullups and/or pulldowns using feedback Hagop Nazarian 1997-08-05
5635856 High speed programmable macrocell with combined path for storage and combinatorial modes Donald A. Krall 1997-06-03
5565791 Method and apparatus for disabling unused sense amplifiers 1996-10-15