Issued Patents All Time
Showing 26–50 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9023707 | Simultaneously forming a dielectric layer in MOS and ONO device regions | Krishnaswamy Ramkumar, Bo Jin | 2015-05-05 |
| 9018693 | Deuterated film encapsulation of nonvolatile charge trap memory device | Krishnaswamy Ramkumar, William Koutny | 2015-04-28 |
| 8993400 | Deuterated film encapsulation of nonvolatile charge trap memory device | Krishnaswamy Ramkumar, William C. Koutny | 2015-03-31 |
| 8871595 | Integration of non-volatile charge trap memory devices and logic CMOS devices | Krishnaswamy Ramkumar, Sagy Levy | 2014-10-28 |
| 8710578 | SONOS stack with split nitride memory layer | Krishnaswamy Ramkumar | 2014-04-29 |
| 8710579 | SONOS stack with split nitride memory layer | Krishnaswamy Ramkumar | 2014-04-29 |
| 8680601 | Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region | Sagy Levy, Krishnaswamy Ramkumar | 2014-03-25 |
| 8679927 | Integration of non-volatile charge trap memory devices and logic CMOS devices | Krishnaswamy Ramkumar, Sagy Levy | 2014-03-25 |
| 8670278 | Method and apparatus for extending the lifetime of a non-volatile trapped-charge memory | Long Hinh | 2014-03-11 |
| 8643124 | Oxide-nitride-oxide stack having multiple oxynitride layers | Sagy Levy, Krishnaswamy Ramkumar, Sam Geha | 2014-02-04 |
| 8637921 | Nitridation oxidation of tunneling layer for improved SONOS speed and retention | Sagy Levy, Krishnaswamy Ramkumar | 2014-01-28 |
| 8614124 | SONOS ONO stack scaling | Sagy Levy | 2013-12-24 |
| 8542541 | Memory architecture having two independently controlled voltage pumps | Ryan T. Hirose, Vijay Srinivasaraghavan, Igor G. Kouznetsov, Paul Fredrick Ruths, Cristinel Zonte +3 more | 2013-09-24 |
| 8536640 | Deuterated film encapsulation of nonvolatile charge trap memory device | Krishnaswamy Ramkumar, William Koutny | 2013-09-17 |
| 8513753 | Photodiode having a buried well region | — | 2013-08-20 |
| 8269287 | Floating gate memory device with increased coupling coefficient | — | 2012-09-18 |
| 8222688 | SONOS stack with split nitride memory layer | Krishnaswamy Ramkumar | 2012-07-17 |
| 8125835 | Memory architecture having two independently controlled voltage pumps | Ryan T. Hirose, Vijay Raghavan, Igor G. Kouznetsov, Paul Fredrick Ruths, Cristinel Zonte +3 more | 2012-02-28 |
| 8093128 | Integration of non-volatile charge trap memory devices and logic CMOS devices | William Koutny, Sam Geha, Igor G. Kouznetsov, Krishnaswamy Ramkumar, Sagy Levy +2 more | 2012-01-10 |
| 8071453 | Method of ONO integration into MOS flow | Krishnaswamy Ramkumar, Bo Jin | 2011-12-06 |
| 8045373 | Method and apparatus for programming memory cell array | Cynthia Ratnakumar | 2011-10-25 |
| 7969804 | Memory architecture having a reference current generator that provides two reference currents | Ryan T. Hirose, Vijay Srinivasaraghavan, Igor G. Kouznetsov, Paul Fredrick Ruths, Cristinel Zonte +3 more | 2011-06-28 |
| 7903458 | Method and apparatus for reduction of bit-line disturb and soft-erase in a trapped-charge memory | — | 2011-03-08 |
| 7881118 | Sense transistor protection for memory programming | — | 2011-02-01 |
| 7859904 | Three cycle memory programming | Cynthia Ratnakumar | 2010-12-28 |