Issued Patents All Time
Showing 26–50 of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7516109 | Automatically deriving logical, arithmetic and timing dependencies | — | 2009-04-07 |
| 7451280 | External memory controller node | Paul L. Master | 2008-11-11 |
| 7225301 | External memory controller node | Paul L. Master | 2007-05-29 |
| 6820068 | System and method for verifying logical, arithmetic and timing dependencies of system behaviors using constraint calculus analysis | — | 2004-11-16 |
| 6292021 | FPGA structure having main, column and sector reset lines | Martin Mason, Robert Brian Luking | 2001-09-18 |
| 6167559 | FPGA structure having main, column and sector clock lines | Martin Mason, Robert Brian Luking | 2000-12-26 |
| 6026227 | FPGA logic cell internal structure including pair of look-up tables | Martin Mason, Robert Brian Luking | 2000-02-15 |
| 6014509 | Field programmable gate array having access to orthogonal and diagonal adjacent neighboring cells | Martin Mason, Robert Brian Luking | 2000-01-11 |
| 5894565 | Field programmable gate array with distributed RAM and increased cell utilization | Martin Mason, Robert Brian Luking | 1999-04-13 |
| 5717346 | Low skew multiplexer network and programmable array clock/reset application thereof | Scott Whitney Gould, Frank Ray Keyser, III, Brian Worth, Terrance John Zittritsch | 1998-02-10 |
| 5703498 | Programmable array clock/reset resource | Scott Whitney Gould, Frank Ray Keyser, III, Brian Worth, Terrance John Zittritsch | 1997-12-30 |
| 5652529 | Programmable array clock/reset resource | Scott Whitney Gould, Frank Ray Keyser, III, Brian Worth, Terrance John Zittritsch | 1997-07-29 |
| 5504931 | Method and apparatus for comparing data sets | — | 1996-04-02 |
| 5430886 | Method and apparatus for motion estimation | — | 1995-07-04 |
| 5298805 | Versatile and efficient cell-to-local bus interface in a configurable logic array | Tim Garverick, Jim Sutherland, Sanjay Popli, Venkata Alturi, Arthur E. Smith +7 more | 1994-03-29 |
| 5296759 | Diagonal wiring between abutting logic cells in a configurable logic array | Jim Sutherland, Sanjay Popli, Venkata Alturi | 1994-03-22 |
| 5245227 | Versatile programmable logic cell for use in configurable logic arrays | Rafael C. Camarota | 1993-09-14 |
| 5218240 | Programmable logic cell and array with bus repeaters | Rafael C. Camarota, Walford W. Ho, Edward H. Browder | 1993-06-08 |
| 5155389 | Programmable logic cell and array | — | 1992-10-13 |
| 5144166 | Programmable logic cell and array | Rafael C. Camarota, Walford W. Ho, Edward H. Browder | 1992-09-01 |
| 5089973 | Programmable logic cell and array | — | 1992-02-18 |
| 5019736 | Programmable logic cell and array | — | 1991-05-28 |
| 4918440 | Programmable logic cell and array | — | 1990-04-17 |
| 4845633 | System for programming graphically a programmable, asynchronous logic cell and array | — | 1989-07-04 |
| 4700187 | Programmable, asynchronous logic cell and array | — | 1987-10-13 |