Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7565461 | Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers | Jon M. Huppenthal, Lee A. Burton | 2009-07-21 |
| 7421524 | Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format | Jon M. Huppenthal, Lee A. Burton | 2008-09-02 |
| 7373440 | Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format | Jon M. Huppenthal, Lee A. Burton | 2008-05-13 |
| 7197575 | Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers | Jon M. Huppenthal, Lee A. Burton | 2007-03-27 |
| 7003593 | Computer system architecture and memory controller for close-coupling within a hybrid processing system utilizing an adaptive processor interface port | Jon M. Huppenthal, Lee A. Burton | 2006-02-21 |
| RE37980 | Bus-to-bus bridge in computer system, with fast burst memory range | Bassam N. Elkhoury, Christopher J. Pettey, Dwight D. Riley, Brian S. Hausauer | 2003-02-04 |
| 6449677 | Method and apparatus for multiplexing and demultiplexing addresses of registered peripheral interconnect apparatus | Sompong Paul Olarig, Kenneth A. Jansen, Dwight D. Riley | 2002-09-10 |
| 6148359 | Bus-to-bus bridge in computer system, with fast burst memory range | Bassam N. Elkhoury, Christopher J. Pettey, Dwight D. Riley, Brian S. Hausauer | 2000-11-14 |
| 6098134 | "Lock protocol for PCI bus using an additional ""superlock"" signal on the system bus" | Peter Michels, Christopher J. Pettey, Brian S. Hausauer | 2000-08-01 |
| 6085274 | Computer system with bridges having posted memory write buffers | — | 2000-07-04 |
| 5881253 | Computer system using posted memory write buffers in a bridge to implement system management mode | — | 1999-03-09 |
| 5870567 | Delayed transaction protocol for computer system bus | Brian S. Hausauer, Christopher J. Pettey | 1999-02-09 |
| 5835741 | Bus-to-bus bridge in computer system, with fast burst memory range | Bassam N. Elkhoury, Christopher J. Pettey, Dwight D. Riley, Brian S. Hausauer | 1998-11-10 |
| 5832243 | Computer system implementing a stop clock acknowledge special cycle | — | 1998-11-03 |
| 5659789 | Stopclock toggle system for powering two CPUs from a regulator only sized for one CPU | Brian S. Hausauer | 1997-08-19 |