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USPTO Patent Rankings Data through Dec 31, 2025
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Thomas R. Seeman — 15 Patents

CCCompaq Computer: 9 patents #105 of 1,604Top 7%
SCSrc Computers: 5 patents #6 of 20Top 30%
CGCompaq Information Technologies Group: 1 patents #84 of 407Top 25%
Tomball, TX: #73 of 577 inventorsTop 15%
Texas: #9,849 of 125,132 inventorsTop 8%
Overall (All Time): #307,048 of 4,157,543Top 8%
15 Patents All Time
Thomas R. Seeman has been granted 15 US patents while listed as an inventor at Compaq Computer. The first was granted in 1997 and the most recent in July 2009. Thomas R. Seeman ranks #307,048 of 4,157,543 US inventors in our database (top 7.4%). Patent records list Thomas R. Seeman in Tomball, TX, US.

Patents per Year

Patents granted per year, 1997 to 2009Bar chart with a peak of 3 patents in 2000.peak 31997: 1 patents19971998: 2 patents19981999: 2 patents19992000: 3 patents20002002: 1 patents20022003: 1 patents20032006: 1 patents20062007: 1 patents20072008: 2 patents20082009: 1 patents2009

Issued Patents All Time

Showing 1–15 of 15 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
7565461 Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers Jon M. Huppenthal, Lee A. Burton 2009-07-21
7421524 Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format Jon M. Huppenthal, Lee A. Burton 2008-09-02
7373440 Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format Jon M. Huppenthal, Lee A. Burton 2008-05-13
7197575 Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers Jon M. Huppenthal, Lee A. Burton 2007-03-27
7003593 Computer system architecture and memory controller for close-coupling within a hybrid processing system utilizing an adaptive processor interface port Jon M. Huppenthal, Lee A. Burton 2006-02-21
RE37980 Bus-to-bus bridge in computer system, with fast burst memory range Bassam N. Elkhoury, Christopher J. Pettey, Dwight D. Riley, Brian S. Hausauer 2003-02-04
6449677 Method and apparatus for multiplexing and demultiplexing addresses of registered peripheral interconnect apparatus Sompong Paul Olarig, Kenneth A. Jansen, Dwight D. Riley 2002-09-10 $20,407,000
6148359 Bus-to-bus bridge in computer system, with fast burst memory range Bassam N. Elkhoury, Christopher J. Pettey, Dwight D. Riley, Brian S. Hausauer 2000-11-14 $187,740,000
6098134 "Lock protocol for PCI bus using an additional ""superlock"" signal on the system bus" Peter Michels, Christopher J. Pettey, Brian S. Hausauer 2000-08-01 $44,998,000
6085274 Computer system with bridges having posted memory write buffers 2000-07-04
5881253 Computer system using posted memory write buffers in a bridge to implement system management mode 1999-03-09 $136,831,000
5870567 Delayed transaction protocol for computer system bus Brian S. Hausauer, Christopher J. Pettey 1999-02-09 $155,737,000
5835741 Bus-to-bus bridge in computer system, with fast burst memory range Bassam N. Elkhoury, Christopher J. Pettey, Dwight D. Riley, Brian S. Hausauer 1998-11-10 $79,274,000
5832243 Computer system implementing a stop clock acknowledge special cycle 1998-11-03 $112,239,000
5659789 Stopclock toggle system for powering two CPUs from a regulator only sized for one CPU Brian S. Hausauer 1997-08-19 $143,346,000