Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8809964 | Method of adjusting the threshold voltage of a transistor by a buried trapping layer | Francois Andrieu, Emmanuel Augendre, Laurent Clavelier | 2014-08-19 |
| 7951659 | Method for simultaneously tensile and compressive straining the channels of NMOS and PMOS transistors respectively | Younes Lamrani, Jean-Charles Barbe | 2011-05-31 |
| 7947564 | Method of fabricating a mixed microtechnology structure and a structure obtained thereby | Hubert Moriceau, Marc Zussy | 2011-05-24 |
| 7879690 | Method of fabricating a microelectronic structure of a semiconductor on insulator type with different patterns | Emmanuel Augendre, Thomas Ernst, Hubert Moriceau | 2011-02-01 |
| 7422958 | Method of fabricating a mixed substrate | Fabrice Letertre | 2008-09-09 |