Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8035038 | Method for fabricating a printed circuit board having a coaxial via | Wheling Cheng, Roger Karam | 2011-10-11 |
| 7574687 | Method and system to optimize timing margin in a system in package module | Wheling Cheng | 2009-08-11 |
| 7404250 | Method for fabricating a printed circuit board having a coaxial via | Wheling Cheng, Roger Karam | 2008-07-29 |
| 7185821 | Method and apparatus for delivering high-current power and ground voltages using top side of chip package substrate | Yida Zou, Luca Cafiero, Gary L. Myers, Bobby Parizi, Hsing-Sheng Liang | 2007-03-06 |
| 7154761 | Techniques for distributing current in a backplane assembly and methods for making the same | Irfan Elahi | 2006-12-26 |
| 7098408 | Techniques for mounting an area array package to a circuit board using an improved pad layout | Lekhanh Dang | 2006-08-29 |
| 7053314 | Methods and apparatus for providing a signal to a circuit board component | — | 2006-05-30 |
| 6914780 | Methods and apparatus for cooling a circuit board component using a heat pipe assembly | Bangalore J. Shanker, Yida Zou | 2005-07-05 |
| 6204712 | Method and apparatus for clock uncertainty minimization | — | 2001-03-20 |
| 6157250 | Method and apparatus for clock uncertainty minimization with a clean power source | — | 2000-12-05 |
| 6157251 | Method and apparatus for clock uncertainty minimization | — | 2000-12-05 |
| 6081106 | Voltage setpoint error reduction | — | 2000-06-27 |
| 6069539 | VTT power distribution system | David K. Sanders | 2000-05-30 |
| 6052012 | Method and apparatus for clock uncertainly minimization | — | 2000-04-18 |