Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11294632 | Multiplication accumulating device and method thereof | Che-Wei Tung | 2022-04-05 |
| 9477258 | Clock tree in circuit having a power-mode control circuit to determine a first delay time and a second delay time | Yow-Tyng Nieh, Shih-Chieh Chang, Chung-Han Chou | 2016-10-25 |
| 8086982 | Methods and systems for reducing clock skew in a gated clock tree | Chia-Ming Chang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang, Yu-Sheng Lu | 2011-12-27 |
| 7904874 | Opposite-phase scheme for peak current reduction | Yow-Tyng Nieh, Sheng-Yu Hsu, Yeong-Jar Chang | 2011-03-08 |
| 7739625 | Method for controlling peak current of a circuit having a plurality of registers | Yow-Tyng Nieh, Chia-Ming Chang | 2010-06-15 |
| 7352212 | Opposite-phase scheme for peak current reduction | Yow-Tyng Nieh, Sheng-Yu Hsu, Yeong-Jar Chang | 2008-04-01 |