Issued Patents All Time
Showing 26–30 of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6306715 | Method to form smaller channel with CMOS device by isotropic etching of the gate materials | Lap Chan, Elgin Quek, Ravi Sundaresan, Yang Pan, Ying-Keung Leung +2 more | 2001-10-23 |
| 6306741 | Method of patterning gate electrodes with high K gate dielectrics | Xia Li, Yun Zhang | 2001-10-23 |
| 6303449 | Method to form self-aligned elevated source/drain by selective removal of gate dielectric in the source/drain region followed by poly deposition and CMP | Yang Pan, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan +2 more | 2001-10-16 |
| 6300177 | Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials | Ravi Sundaresan, Yang Pan, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng +2 more | 2001-10-09 |
| 6197691 | Shallow trench isolation process | — | 2001-03-06 |