Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7797140 | Generalizations of adjoint networks techniques for RLC interconnects model-order reductions | Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng | 2010-09-14 |
| 7600206 | Method of estimating the signal delay in a VLSI circuit | Chao-Hsuan Hsu, Chia-Chi Chu, Wu-Shiung Feng | 2009-10-06 |
| 7509243 | Method of determining high-speed VLSI reduced-order interconnect by non-symmetric lanczos algorithm | Chia-Chi Chu, Wu-Shiung Feng | 2009-03-24 |
| 7398499 | Method of searching paths suffering from the electrostatic discharge in the process of an integrated circuit design | Chao-Yi Cho, Chia-Chi Chu, Wu-Shiung Feng | 2008-07-08 |
| 7254790 | Method of moment computations in R(L)C interconnects of high speed VLSI with resistor loops | Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng | 2007-08-07 |
| 7216322 | Clock tree synthesis for low power consumption and low clock skew | Chao-Kai Chang, Chia-Chi Chu, Wu-Shiung Feng | 2007-05-08 |
| 7124381 | Method of estimating crosstalk noise in lumped RLC coupled interconnects | Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng | 2006-10-17 |
| 7017130 | Method of verification of estimating crosstalk noise in coupled RLC interconnects with distributed line in nanometer integrated circuits | Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng | 2006-03-21 |