Issued Patents All Time
Showing 26–35 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 4768148 | Read in process memory apparatus | George J. Barlow | 1988-08-30 |
| 4764862 | Resilient bus system | George J. Barlow | 1988-08-16 |
| 4763243 | Resilient bus system | George J. Barlow | 1988-08-09 |
| 4724519 | Channel number priority assignment apparatus | George J. Barlow, Elmer W. Carroll | 1988-02-09 |
| 4695943 | Multiprocessor shared pipeline cache memory with split cycle and concurrent utilization | Thomas F. Joyce | 1987-09-22 |
| 4686621 | Test apparatus for testing a multilevel cache system with graceful degradation capability | Robert V. Ledoux, Virendra S. Negi | 1987-08-11 |
| 4667288 | Enable/disable control checking apparatus | Robert V. Ledoux, Virendra S. Negi | 1987-05-19 |
| 4575792 | Shared interface apparatus for testing the memory sections of a cache unit | — | 1986-03-11 |
| 4562536 | Directory test error mode control apparatus | Robert V. Ledoux, Virendra S. Negi | 1985-12-31 |
| 4464717 | Multilevel cache system with graceful degradation capability | Edwin P. Fisher, John L. Curley | 1984-08-07 |