QS

Quincy Kun-Hsu Shen

AS Axis Systems: 3 patents #3 of 11Top 30%
CS Cadence Design Systems: 3 patents #541 of 2,263Top 25%
📍 Union City, CA: #293 of 1,177 inventorsTop 25%
🗺 California: #93,399 of 386,348 inventorsTop 25%
Overall (All Time): #854,673 of 4,157,543Top 25%
6
Patents All Time

Issued Patents All Time

Showing 1–6 of 6 patents

Patent #TitleCo-InventorsDate
9195784 Common shared memory in a verification system Ping-Sheng Tseng, Sharon Sheau-Pyng Lin, Mike Mon Yen Tsai, Steven Wang 2015-11-24
8244512 Method and apparatus for simulating a circuit using timing insensitive glitch-free (TIGF) logic Ping-Sheng Tseng, Sharon Sheau-Pyng Lin, Mike Mon Yen Tsai, Steven Wang 2012-08-14
8161502 Method and apparatus for implementing a task-based interface in a logic verification system Song Peng, Ping-Sheng Tseng 2012-04-17
6321366 Timing-insensitive glitch-free logic system and method Ping-Sheng Tseng, Sharon Sheau-Pyng Lin 2001-11-20
6134516 Simulation server system and method Steven Wang, Ping-Sheng Tseng, Sharon Sheau-Pyng Lin, Ren-Song Tsay, Richard Yachyang Sun +1 more 2000-10-17
6009256 Simulation/emulation system and method Ping-Sheng Tseng, Sharon Sheau-Pyng Lin, Richard Yachyang Sun, Mike Mon Yen Tsai, Ren-Song Tsay +1 more 1999-12-28