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Vector processor utilizing massively fused operations |
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Apparatuses, methods, and systems for vector processor architecture having an array of identical circuit blocks |
Joseph Williams, Jeroen Leijten, Harm Peters, Eugene Scuteri |
2021-07-27 |
| 7426247 |
Multi-channel serdes receiver for chip-to-chip and backplane interconnects and method of operation thereof |
Fuji Yang, Patrick Larsson |
2008-09-16 |
| 7158587 |
Multi-channel serdes receiver for chip-to-chip and backplane interconnects and method of operation thereof |
Fuji Yang, Patrick Larsson |
2007-01-02 |
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Packet network interface |
Vijay Kumar, Horng-Dar Lin, Philippe Oechslin, Edward Joseph Ouellette, III |
2003-02-11 |
| 6292384 |
Access structure for high density read only memory |
— |
2001-09-18 |
| 6185121 |
Access structure for high density read only memory |
— |
2001-02-06 |
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Method and apparatus for generating a clock signal from a plurality of clock phases |
Patrik Larsson |
2000-06-27 |
| 5898689 |
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Vijay Kumar, Horng-Dar Lin, Philippe Oechslin, Edward Joseph Ouellette, III |
1999-04-27 |
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Static random access memory sense amplifier |
Bryan D. Ackland |
1997-02-18 |
| 4891803 |
Packet switching network |
Alan Huang, Scott C. Knauer, Charles W. Rutledge, Sheng-Liu Lin, Maurice N. Ransom +1 more |
1990-01-02 |
| 4760543 |
Orthogonal transform processor |
Adrianus Ligtenberg |
1988-07-26 |
| 4592019 |
Bus oriented LIFO/FIFO memory |
Alan Huang |
1986-05-27 |