BT

Bo Tang

Apple: 15 patents #2,169 of 18,612Top 15%
Oracle: 5 patents #2,536 of 14,854Top 20%
UN Unknown: 2 patents #12,644 of 83,584Top 20%
NL Nuctech Company Limited: 2 patents #232 of 517Top 45%
ZU Zhejiang University: 1 patents #773 of 2,379Top 35%
ZT Zte: 1 patents #1,433 of 3,593Top 40%
GE: 1 patents #19,878 of 36,430Top 55%
Huawei: 1 patents #8,196 of 15,535Top 55%
DE Delta Electronics: 1 patents #1,366 of 2,746Top 50%
BM Beijing Kt Micro: 1 patents #11 of 19Top 60%
Honda Motor Co.: 1 patents #12,035 of 21,052Top 60%
Overall (All Time): #71,513 of 4,157,543Top 2%
42
Patents All Time

Issued Patents All Time

Showing 26–42 of 42 patents

Patent #TitleCo-InventorsDate
8791743 Balanced level shifter with wide operation range Huaimin Li, Ajay Bhatia 2014-07-29
8754692 Low power and soft error hardened dual edge triggered flip flop 2014-06-17
8726216 Area efficient power switch Shingo Suzuki, Karthik Rajagopal 2014-05-13
8635503 Scan latch with phase-free scan enable Edgardo F. Klass 2014-01-21
8564467 Generating an adjustable signal Pei Yang, Rongrong Bai, Jianting Wang, Yaoli Jiang, Dianyu Chen +8 more 2013-10-22
8558594 Reduced frequency clock delivery with local recovery Andrew J. Demas 2013-10-15
8493118 Low power scannable latch Honkai Tam 2013-07-23
8332698 Scan latch with phase-free scan enable Edgardo F. Klass 2012-12-11
8305125 Low latency synchronizer circuit Edgardo F. Klass 2012-11-06
8275504 Stabilization apparatus and method for stabling load voltage of vehicle Chin-Hou Chen, Ko-Yu Hsiao 2012-09-25
8181074 Soft error recoverable storage element and soft error protection technique 2012-05-15
8134387 Self-gating synchronizer Edgardo F. Klass 2012-03-13
7977976 Self-gating synchronizer Edgardo F. Klass 2011-07-12
7843244 Low latency synchronizer circuit Edgardo F. Klass 2010-11-30
7629815 Low-power semi-dynamic flip-flop with smart keeper Ilyas Elkin, Georgios Konstadinidis 2009-12-08
7088144 Conditional precharge design in staticized dynamic flip-flop with clock enable Edgardo F. Klass, Geoffrey Pilling 2006-08-08
6741113 Modified high speed flop design with self adjusting, data selective, evaluation window Edgardo F. Klass 2004-05-25