Issued Patents All Time
Showing 26–36 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7543221 | Method and apparatus for reducing false error detection in a redundant multi-threaded system | Shubhendu Sekhar Mukherjee, Joel S. Emer, Christopher T. Weaver, Michael J. Smith | 2009-06-02 |
| 7444497 | Managing external memory updates for fault detection in redundant multithreading systems using speculative memory support | Shubhendu Sekhar Mukherjee, Joel S. Emer, Christopher T. Weaver | 2008-10-28 |
| 7386756 | Reducing false error detection in a microprocessor by tracking instructions neutral to errors | Joel S. Emer, Shubhendu Sekhar Mukherjee, Christopher T. Weaver | 2008-06-10 |
| 7373548 | Hardware recovery in a multi-threaded architecture | Shubhendu Sekhar Mukherjee, Joel S. Emer | 2008-05-13 |
| 7353365 | Implementing check instructions in each thread within a redundant multithreading environments | Shubhendu Sekhar Mukherjee, Joel S. Emer, Christopher T. Weaver | 2008-04-01 |
| 7308607 | Periodic checkpointing in a redundantly multi-threaded architecture | Shubhendu Sekhar Mukherjee, Joel S. Emer | 2007-12-11 |
| 7243262 | Incremental checkpointing in a multi-threaded architecture | Shubhendu Sekhar Mukherjee, Joel S. Emer | 2007-07-10 |
| 6854075 | Simultaneous and redundantly threaded processor store instruction comparator | Shubhendu Sekhar Mukherjee | 2005-02-08 |
| 6792525 | Input replicator for interrupts in a simultaneous and redundantly threaded processor | Shubhendu Sekhar Mukherjee | 2004-09-14 |
| 6598122 | Active load address buffer | Shubhendu Sekhar Mukherjee | 2003-07-22 |
| 5951657 | Cacheable interface control registers for high speed data transfer | David A. Wood, Shubhendu Sekhar Mukherjee, Babak Falsafi, Mark D. Hill, Robert Pfile | 1999-09-14 |