Issued Patents All Time
Showing 26–50 of 91 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9606936 | Generalized control registers | Andy Kegel, Tony Asaro, Philip Ng | 2017-03-28 |
| 9535849 | IOMMU using two-level address translation for I/O and computation offload devices on a peripheral interconnect | Andrew G. Kegel, Stephen D. Glaser | 2017-01-03 |
| 9448930 | Memory heaps in a memory model for a unified computing system | Anthony Asaro, Kevin Normoyle | 2016-09-20 |
| 9430391 | Managing coherent memory between an accelerated processing device and a central processing unit | Anthony Asaro, Kevin Normoyle | 2016-08-30 |
| 9424199 | Virtual input/output memory management unit within a guest virtual machine | Andrew G. Kegel | 2016-08-23 |
| 9251001 | Channel rotating error correction code | Michael J. Osborn, David E. Mayhew | 2016-02-02 |
| 9253287 | Speculation based approach for reliable message communications | Venkata Krishnan, David E. Mayhew | 2016-02-02 |
| 9176795 | Graphics processing dispatch from user mode | Rex Eldon McCrary, Michael Clair Houston, Philip J. Rogers, Gongxian Jeffrey Cheng, Paul Blinzer | 2015-11-03 |
| 9176794 | Graphics compute process scheduling | Jeffrey G. Cheng, Paul Blinzer, Leendert Peter Van Doorn | 2015-11-03 |
| 9154451 | Systems and methods for sharing devices in a virtualization environment | Anton Chernoff, Venkata Krishnan, David E. Mayhew, Michael J. Osborn | 2015-10-06 |
| 9152571 | All invalidate approach for memory management units | Andrew G. Kegel, Anthony Asaro | 2015-10-06 |
| 9137173 | Devices and methods for interconnecting server nodes | David E. Mayhew, Michael J. Osborn | 2015-09-15 |
| 9116809 | Memory heaps in a memory model for a unified computing system | Anthony Asaro, Kevin Normoyle | 2015-08-25 |
| 9069698 | Channel rotating error correction code | Michael J. Osborn, David E. Mayhew | 2015-06-30 |
| 9009419 | Shared memory space in a unified memory model | Anthony Asaro, Kevin Normoyle, Mark Fowler | 2015-04-14 |
| 8984511 | Visibility ordering in a memory model for a unified computing system | Anthony Asaro, Kevin Normoyle | 2015-03-17 |
| 8966461 | Vector width-aware synchronization-elision for vector processors | Benedict R. Gaster, Lee W. Howes | 2015-02-24 |
| 8933947 | Reading a local memory of a processing unit | David Glen, Philip J. Rogers, Gordon Caruk, Gongxian Jeffrey Cheng, Stephen P. Thompson +1 more | 2015-01-13 |
| 8935475 | Cache management for memory operations | Anthony Asaro, Kevin Normoyle, Norman Rubin, Mark Fowler | 2015-01-13 |
| 8929220 | Processing system using virtual network interface controller addressing as flow control metadata | Mauricio Breternitz, Anton Chernoff | 2015-01-06 |
| 8879301 | Method and apparatus for controlling state information retention in an apparatus | David E. Mayhew, Michael Ignatowski | 2014-11-04 |
| 8875256 | Data flow processing in a network environment | David E. Mayhew, Michael J. Osborn | 2014-10-28 |
| 8868672 | Server node interconnect devices and methods | David E. Mayhew, Michael J. Osborn | 2014-10-21 |
| 8842126 | Methods and systems to facilitate operation in unpinned memory | Warren Fritz Kruger, Philip J. Rogers | 2014-09-23 |
| 8832382 | Sub page and page memory management apparatus and method | David E. Mayhew | 2014-09-09 |