Issued Patents All Time
Showing 26–45 of 45 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6629308 | Method for managing database models for reduced programmable logic device components | — | 2003-09-30 |
| 6625787 | Method and apparatus for timing management in a converted design | Andy H. Gan | 2003-09-23 |
| 6526563 | Method for improving area in reduced programmable logic devices | — | 2003-02-25 |
| 6515509 | Programmable logic device structures in standard cell devices | — | 2003-02-04 |
| 6490707 | Method for converting programmable logic devices into standard cell devices | — | 2002-12-03 |
| 6370601 | Intelligent direct memory access controller providing controlwise and datawise intelligence for DMA transfers | — | 2002-04-09 |
| 6353921 | Hardwire logic device emulating any of two or more FPGAs | Edwin S. Law, Kiran B. Buch, Raymond C. Pang | 2002-03-05 |
| 6308309 | Place-holding library elements for defining routing paths | Andy H. Gan | 2001-10-23 |
| 6226779 | Programmable IC with gate array core and boundary scan capability | Kiran B. Buch, Edwin S. Law | 2001-05-01 |
| 6202106 | Method for providing specific knowledge of a structure of parameter blocks to an intelligent direct memory access controller | — | 2001-03-13 |
| 6134517 | Method of implementing a boundary scan chain | Kiran B. Buch, Raymond C. Pang, Edwin S. Law | 2000-10-17 |
| 6120551 | Hardwire logic device emulating an FPGA | Edwin S. Law, Kiran B. Buch, Raymond C. Pang | 2000-09-19 |
| 6078735 | System and method for generating memory initialization logic in a target device with memory initialization bits from a programmable logic device | — | 2000-06-20 |
| 6071314 | Programmable I/O cell with dual boundary scan | Kiran B. Buch, Edwin S. Law | 2000-06-06 |
| 6018624 | Method to back annotate programmable logic device design files based on timing information of a target technology | — | 2000-01-25 |
| 5991908 | Boundary scan chain with dedicated programmable routing | Kiran B. Buch, Raymond C. Pang, Edwin S. Law | 1999-11-23 |
| 5949983 | Method to back annotate programmable logic device design files based on timing information of a target technology | — | 1999-09-07 |
| 5870586 | Configuration emulation of a programmable logic device | — | 1999-02-09 |
| 5815405 | Method and apparatus for converting a programmable logic device representation of a circuit into a second representation of the circuit | — | 1998-09-29 |
| 5752006 | Configuration emulation of a programmable logic device | — | 1998-05-12 |