Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12019716 | Multimedia content recognition with local and cloud-assisted machine learning | Yong Li, Xuemin Chen, Prashant Katre | 2024-06-25 |
| 11544354 | System for secure provisioning and enforcement of system-on-chip (SOC) features | Yong Li, Sherman (Xuemin) Chen, Abbas Saadat, Fabian Russo, Dexter Bayani +1 more | 2023-01-03 |
| 9538199 | Data transmission across independent streams | Wade Wan, Rajesh Mamidwar, Xuemin Chen, Marcus Kellerman | 2017-01-03 |
| 9001728 | Data transmission across independent streams | Wade Wan, Rajesh Mamidwar, Xuemin Chen, Marcus Kellerman | 2015-04-07 |
| 8587600 | System and method for cache-based compressed display data storage | Kenneth J. Kotlowski, Willard S. Briggs | 2013-11-19 |
| 8368710 | Data block transfer to cache | — | 2013-02-05 |
| 8304698 | Thermal throttling of peripheral components in a processing device | — | 2012-11-06 |
| 8065457 | Delayed memory access request arbitration | — | 2011-11-22 |
| 7535474 | System and method for rotating rasterized image data | Kevin A. Scholander | 2009-05-19 |
| 7519883 | Method of configuring a system and system therefor | Daniel E. Daugherty, Steven J. Kommrusch | 2009-04-14 |
| 7426621 | Memory access request arbitration | Steven J. Kommrusch | 2008-09-16 |
| 7398362 | Programmable interleaving in multiple-bank memories | — | 2008-07-08 |
| 7185128 | System and method for machine specific register addressing in external devices | Kenneth J. Kotlowski | 2007-02-27 |
| 7143225 | Apparatus and method for viewing data processor bus transactions on address pins during memory idle cycles | Redentor Valencia | 2006-11-28 |
| 7107494 | Bus architecture using debug packets to monitor transactions on an internal data processor bus | — | 2006-09-12 |
| 7043593 | Apparatus and method for sending in order data and out of order data on a data bus | Kenneth J. Kotlowski | 2006-05-09 |
| 7020741 | Apparatus and method for isochronous arbitration to schedule memory refresh requests | — | 2006-03-28 |
| 7007188 | Precision bypass clock for high speed testing of a data processor | Steven J. Kommrusch | 2006-02-28 |
| 6924810 | Hierarchical texture cache | — | 2005-08-02 |
| 6912611 | Split transactional unidirectional bus architecture and method of operation | Kenneth J. Kotlowski | 2005-06-28 |
| 6813673 | Bus arbitrator supporting multiple isochronous streams in a split transactional unidirectional bus architecture and method of operation | Kenneth J. Kotlowski | 2004-11-02 |
| 6801207 | Multimedia processor employing a shared CPU-graphics cache | Carl Dietz, David F. Bremner, David T. Harper, III | 2004-10-05 |
| 6785758 | System and method for machine specific register addressing in a split transactional unidirectional bus architecture | Kenneth J. Kotlowski | 2004-08-31 |
| 6763415 | Speculative bus arbitrator and method of operation | — | 2004-07-13 |
| 6591347 | Dynamic replacement technique in a shared cache | Rajeev Jayavant | 2003-07-08 |