Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11990713 | Connector positioning system and method | Ryan Albright, Devarshi Patel, Chris Fox, Mark White, Susheela Narasimhan +2 more | 2024-05-21 |
| 10817043 | System and method for entering and exiting sleep mode in a graphics subsystem | Thomas E. Dewey, David Wyatt | 2020-10-27 |
| 7256792 | Method and apparatus for sampling non-power of two dimension texture maps | Walter E. Donovan | 2007-08-14 |
| 7136071 | Method and apparatus for sampling non-power of two dimension texture maps | Walter E. Donovan | 2006-11-14 |
| 6967659 | Circuitry and systems for performing two-dimensional motion compensation using a three-dimensional pipeline and methods of operating the same | David W. Nuechterlein | 2005-11-22 |
| 6718439 | Cache memory and method of operation | — | 2004-04-06 |
| 6591347 | Dynamic replacement technique in a shared cache | Brett A. Tischler | 2003-07-08 |
| 6434688 | Method and apparatus for providing and maximizing concurrent operations in a shared memory system which includes display memory | William Desi Rhoden | 2002-08-13 |
| RE36839 | Method and apparatus for reducing power consumption in digital electronic circuits | Laura E. Simmons | 2000-08-29 |
| 5826048 | PCI bus with reduced number of signals | Morgan J. Dempsey | 1998-10-20 |
| 5717875 | Computing device having semi-dedicated high speed bus | Huzefa H. Cutlerywala, Judson A. Lehman | 1998-02-10 |
| 5642136 | Method and apparatus for screen refresh bandwidth reduction for video display modes | William Desi Rhoden | 1997-06-24 |
| 5585745 | Method and apparatus for reducing power consumption in digital electronic circuits | Laura E. Simmons | 1996-12-17 |
| 5454076 | Method and apparatus for simultaneously minimizing storage and maximizing total memory bandwidth for a repeating pattern | Bradley W. Cain, William Desi Rhoden | 1995-09-26 |