Issued Patents All Time
Showing 51–63 of 63 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9201777 | Quality of service support using stacked memory device with logic die | Lisa R. Hsu, Gabriel H. Loh, Michael Ignatowski | 2015-12-01 |
| 9189399 | Stack cache management and coherence techniques | Lena E. Olson, Yasuko Eckert | 2015-11-17 |
| 9183055 | Selecting a resource from a set of resources for performing an operation | Mithuna S. Thottethodi, James M. O'Connor, Mauricio Breternitz, Lisa R. Hsu, Gabriel H. Loh +1 more | 2015-11-10 |
| 9170948 | Cache coherency using die-stacked memory device with logic die | Gabriel H. Loh, Lisa R. Hsu, Michael Ignatowski, Michael Schulte | 2015-10-27 |
| 9135185 | Die-stacked memory device providing data translation | Gabriel H. Loh, James M. O'Connor, Michael Ignatowski, Michael Schulte, Lisa R. Hsu +1 more | 2015-09-15 |
| 9075730 | Mechanisms to bound the presence of cache blocks with specific properties in caches | Mithuna S. Thottethodi, Gabriel H. Loh, James M. O'Connor, Yasuko Eckert | 2015-07-07 |
| 9015448 | Message broadcast with router bypassing | Tushar Krishna, Steven K. Reinhardt | 2015-04-21 |
| 9003130 | Multi-core processing device with invalidation cache tags and methods | James M. O'Connor | 2015-04-07 |
| 8984255 | Processing device with address translation probing and methods | Lisa R. Hsu, Nuwan Jayasena, Andrew G. Kegel | 2015-03-17 |
| 8621131 | Uniform multi-chip identification and routing system | Gabriel H. Loh, Jaewoong Chung, Subho Sanjay Chatterjee | 2013-12-31 |
| 7975107 | Processor cache management with software input via an intermediary | Bradley M. Waters | 2011-07-05 |
| 7913040 | Managing working set use of a cache via page coloring | Bradley M. Waters | 2011-03-22 |
| 7747820 | Managing working set use of a cache via page coloring | Bradley M. Waters | 2010-06-29 |