| 7584448 |
Constructing a model of a programmable logic device |
Bart Reynolds, Keith R. Bean, Daniel P. Kirkwood, James F. Barei |
2009-09-01 |
| 7536668 |
Determining networks of a tile module of a programmable logic device |
Bart Reynolds, Keith R. Bean, Daniel P. Kirkwood, James F. Barei |
2009-05-19 |
| 7472370 |
Comparing graphical and netlist connections of a programmable logic device |
Bart Reynolds, Keith R. Bean, Daniel P. Kirkwood, James F. Barei |
2008-12-30 |
| 7451425 |
Determining controlling pins for a tile module of a programmable logic device |
Bart Reynolds, Keith R. Bean, Daniel P. Kirkwood, James F. Barei |
2008-11-11 |
| 7451423 |
Determining indices of configuration memory cell modules of a programmable logic device |
Bart Reynolds, Keith R. Bean, Daniel P. Kirkwood, James F. Barei |
2008-11-11 |
| 7451420 |
Determining reachable pins of a network of a programmable logic device |
Bart Reynolds, Keith R. Bean, Daniel P. Kirkwood, James F. Barei |
2008-11-11 |
| 7451424 |
Determining programmable connections through a switchbox of a programmable logic device |
Bart Reynolds, Keith R. Bean, Daniel P. Kirkwood, James F. Barei |
2008-11-11 |