Issued Patents All Time
Showing 51–73 of 73 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7219183 | Switching apparatus and method for providing shared I/O within a load-store fabric | Asif Khan, Annette Pagan, Richard E. Pekkala, Robert Haskell Utley | 2007-05-15 |
| 7188209 | Apparatus and method for sharing I/O endpoints within a load store fabric by encapsulation of domain information in transaction layer packets | Asif Khan, Annette Pagan, Richard E. Pekkala, Robert Haskell Utley | 2007-03-06 |
| 7174413 | Switching apparatus and method for providing shared I/O within a load-store fabric | Asif Khan, Annette Pagan, Richard E. Pekkala, Robert Haskell Utley | 2007-02-06 |
| 7149817 | Infiniband TM work queue to TCP/IP translation | — | 2006-12-12 |
| 7149819 | Work queue to TCP/IP translation | — | 2006-12-12 |
| 7103064 | Method and apparatus for shared I/O in a load/store fabric | Asif Khan, Annette Pagan, Richard E. Pekkala, Robert Haskell Utley | 2006-09-05 |
| 7099986 | High speed peripheral interconnect apparatus, method and system | Dwight D. Riley | 2006-08-29 |
| 7046668 | Method and apparatus for shared I/O in a load/store fabric | Asif Khan, Annette Pagan, Richard E. Pekkala, Robert Haskell Utley | 2006-05-16 |
| 6816934 | Computer system with registered peripheral component interconnect device for processing extended commands and attributes according to a registered peripheral component interconnect protocol | Dwight D. Riley | 2004-11-09 |
| 6594712 | Inifiniband channel adapter for performing direct DMA between PCI bus and inifiniband link | Lawrence H. Rubin | 2003-07-15 |
| 6557068 | High speed peripheral interconnect apparatus, method and system | Dwight D. Riley | 2003-04-29 |
| RE37980 | Bus-to-bus bridge in computer system, with fast burst memory range | Bassam N. Elkhoury, Dwight D. Riley, Thomas R. Seeman, Brian S. Hausauer | 2003-02-04 |
| 6266731 | High speed peripheral interconnect apparatus, method and system | Dwight D. Riley | 2001-07-24 |
| 6148359 | Bus-to-bus bridge in computer system, with fast burst memory range | Bassam N. Elkhoury, Dwight D. Riley, Thomas R. Seeman, Brian S. Hausauer | 2000-11-14 |
| 6134638 | Memory controller supporting DRAM circuits with different operating speeds | S. Paul Olarig | 2000-10-17 |
| 6098134 | "Lock protocol for PCI bus using an additional ""superlock"" signal on the system bus" | Peter Michels, Thomas R. Seeman, Brian S. Hausauer | 2000-08-01 |
| 6067590 | Data bus agent including a storage medium between a data bus and the bus agent device | Dwight D. Riley | 2000-05-23 |
| 6055590 | Bridge circuit comprising independent transaction buffers with control logic adapted to store overflow data in second buffer when transaction size exceeds the first buffer size | John M. MacLaren | 2000-04-25 |
| 6021480 | Aligning a memory read request with a cache line boundary when the request is for data beginning at a location in the middle of the cache line | — | 2000-02-01 |
| 5903906 | Receiving a write request that allows less than one cache line of data to be written and issuing a subsequent write request that requires at least one cache line of data to be written | — | 1999-05-11 |
| 5872941 | Providing data from a bridge to a requesting device while the bridge is receiving the data | Alan L. Goodrum, John M. MacLaren, Paul R. Culley | 1999-02-16 |
| 5870567 | Delayed transaction protocol for computer system bus | Brian S. Hausauer, Thomas R. Seeman | 1999-02-09 |
| 5835741 | Bus-to-bus bridge in computer system, with fast burst memory range | Bassam N. Elkhoury, Dwight D. Riley, Thomas R. Seeman, Brian S. Hausauer | 1998-11-10 |